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@ -49,6 +49,18 @@
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#include <spm_mcdi.h>
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#include <spm_suspend.h>
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#if !ENABLE_PLAT_COMPAT
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#define MTK_PWR_LVL0 0
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#define MTK_PWR_LVL1 1
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#define MTK_PWR_LVL2 2
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/* Macros to read the MTK power domain state */
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#define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0]
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#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
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#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
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(state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
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#endif
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struct core_context {
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unsigned long timer_data[8];
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unsigned int count;
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@ -219,6 +231,7 @@ static void mt_platform_restore_context(unsigned long mpidr)
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mt_cpu_restore(mpidr);
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}
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#if ENABLE_PLAT_COMPAT
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/*******************************************************************************
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* Private function which is used to determine if any platform actions
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* should be performed for the specified affinity instance given its
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@ -270,11 +283,25 @@ static void plat_affinst_standby(unsigned int power_state)
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wfi();
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}
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}
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#else
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static void plat_cpu_standby(plat_local_state_t cpu_state)
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{
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unsigned int scr;
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scr = read_scr_el3();
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write_scr_el3(scr | SCR_IRQ_BIT);
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isb();
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dsb();
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wfi();
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write_scr_el3(scr);
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}
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#endif
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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* on. The level and mpidr determine the affinity instance.
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******************************************************************************/
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#if ENABLE_PLAT_COMPAT
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static int plat_affinst_on(unsigned long mpidr,
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unsigned long sec_entrypoint,
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unsigned int afflvl,
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@ -308,6 +335,32 @@ static int plat_affinst_on(unsigned long mpidr,
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return rc;
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}
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#else
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static uintptr_t secure_entrypoint;
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static int plat_power_domain_on(unsigned long mpidr)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned long cpu_id;
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unsigned long cluster_id;
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uintptr_t rv;
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cpu_id = mpidr & MPIDR_CPU_MASK;
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cluster_id = mpidr & MPIDR_CLUSTER_MASK;
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if (cluster_id)
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rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
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else
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rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
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mmio_write_32(rv, secure_entrypoint);
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INFO("mt_on[%ld:%ld], entry %x\n",
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cluster_id, cpu_id, mmio_read_32(rv));
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spm_hotplug_on(mpidr);
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return rc;
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}
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#endif
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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@ -321,6 +374,7 @@ static int plat_affinst_on(unsigned long mpidr,
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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#if ENABLE_PLAT_COMPAT
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static void plat_affinst_off(unsigned int afflvl, unsigned int state)
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{
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unsigned long mpidr = read_mpidr_el1();
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@ -343,6 +397,26 @@ static void plat_affinst_off(unsigned int afflvl, unsigned int state)
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trace_power_flow(mpidr, CLUSTER_DOWN);
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}
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}
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#else
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static void plat_power_domain_off(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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/* Prevent interrupts from spuriously waking up this cpu */
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arm_gic_cpuif_deactivate();
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spm_hotplug_off(mpidr);
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trace_power_flow(mpidr, CPU_DOWN);
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Disable coherency if this cluster is to be turned off */
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plat_cci_disable();
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trace_power_flow(mpidr, CLUSTER_DOWN);
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}
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}
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#endif
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be
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@ -356,6 +430,7 @@ static void plat_affinst_off(unsigned int afflvl, unsigned int state)
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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#if ENABLE_PLAT_COMPAT
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static void plat_affinst_suspend(unsigned long sec_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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@ -399,6 +474,47 @@ static void plat_affinst_suspend(unsigned long sec_entrypoint,
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arm_gic_cpuif_deactivate();
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}
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}
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#else
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static void plat_power_domain_suspend(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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unsigned long cluster_id;
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unsigned long cpu_id;
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uintptr_t rv;
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cpu_id = mpidr & MPIDR_CPU_MASK;
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cluster_id = mpidr & MPIDR_CLUSTER_MASK;
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if (cluster_id)
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rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
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else
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rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
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mmio_write_32(rv, secure_entrypoint);
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if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) {
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spm_mcdi_prepare_for_off_state(mpidr, MTK_PWR_LVL0);
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF)
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spm_mcdi_prepare_for_off_state(mpidr, MTK_PWR_LVL1);
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}
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mt_platform_save_context(mpidr);
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/* Perform the common cluster specific operations */
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Disable coherency if this cluster is to be turned off */
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plat_cci_disable();
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}
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if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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disable_scu(mpidr);
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generic_timer_backup();
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spm_system_suspend();
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/* Prevent interrupts from spuriously waking up this cpu */
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arm_gic_cpuif_deactivate();
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}
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}
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#endif
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance has just been powered
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@ -407,6 +523,7 @@ static void plat_affinst_suspend(unsigned long sec_entrypoint,
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* was turned off prior to wakeup and do what's necessary to setup it up
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* correctly.
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******************************************************************************/
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#if ENABLE_PLAT_COMPAT
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static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state)
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{
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unsigned long mpidr = read_mpidr_el1();
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@ -427,12 +544,41 @@ static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state)
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arm_gic_pcpu_distif_setup();
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trace_power_flow(mpidr, CPU_UP);
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}
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#else
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void mtk_system_pwr_domain_resume(void);
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static void plat_power_domain_on_finish(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF);
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if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) &&
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(state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF))
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mtk_system_pwr_domain_resume();
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if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
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plat_cci_enable();
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trace_power_flow(mpidr, CLUSTER_UP);
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}
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if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) &&
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(state->pwr_domain_state[MTK_PWR_LVL2] == MTK_LOCAL_STATE_OFF))
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return;
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/* Enable the gic cpu interface */
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arm_gic_cpuif_setup();
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arm_gic_pcpu_distif_setup();
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trace_power_flow(mpidr, CPU_UP);
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}
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#endif
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance has just been powered
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* on after having been suspended earlier. The level and mpidr determine the
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* affinity instance.
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******************************************************************************/
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#if ENABLE_PLAT_COMPAT
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static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
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{
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unsigned long mpidr = read_mpidr_el1();
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@ -463,12 +609,55 @@ static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
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arm_gic_pcpu_distif_setup();
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}
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#else
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static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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if (state->pwr_domain_state[MTK_PWR_LVL0] == MTK_LOCAL_STATE_RET)
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return;
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if (MTK_SYSTEM_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Enable the gic cpu interface */
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arm_gic_setup();
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arm_gic_cpuif_setup();
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spm_system_suspend_finish();
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enable_scu(mpidr);
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}
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/* Perform the common cluster specific operations */
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF) {
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/* Enable coherency if this cluster was off */
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plat_cci_enable();
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}
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mt_platform_restore_context(mpidr);
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if (MTK_SYSTEM_PWR_STATE(state) != MTK_LOCAL_STATE_OFF) {
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spm_mcdi_finish_for_on_state(mpidr, MTK_PWR_LVL0);
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if (MTK_CLUSTER_PWR_STATE(state) == MTK_LOCAL_STATE_OFF)
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spm_mcdi_finish_for_on_state(mpidr, MTK_PWR_LVL1);
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}
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arm_gic_pcpu_distif_setup();
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}
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#endif
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#if ENABLE_PLAT_COMPAT
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static unsigned int plat_get_sys_suspend_power_state(void)
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{
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/* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */
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return psci_make_powerstate(0, 1, 2);
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}
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#else
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static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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assert(PLAT_MAX_PWR_LVL >= 2);
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for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
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}
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#endif
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/*******************************************************************************
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* MTK handlers to shutdown/reboot the system
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@ -500,6 +689,58 @@ static void __dead2 plat_system_reset(void)
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panic();
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}
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#if !ENABLE_PLAT_COMPAT
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static int plat_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pstate = psci_get_pstate_type(power_state);
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int i;
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assert(req_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Sanity check the requested state */
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if (pstate == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on power level 0
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* Ignore any other power level.
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*/
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if (pwr_lvl != 0)
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return PSCI_E_INVALID_PARAMS;
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req_state->pwr_domain_state[MTK_PWR_LVL0] =
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|
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MTK_LOCAL_STATE_RET;
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|
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} else {
|
|
|
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for (i = 0; i <= pwr_lvl; i++)
|
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|
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|
req_state->pwr_domain_state[i] =
|
|
|
|
|
MTK_LOCAL_STATE_OFF;
|
|
|
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|
}
|
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|
|
|
|
|
|
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|
/*
|
|
|
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|
* We expect the 'state id' to be zero.
|
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|
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|
*/
|
|
|
|
|
if (psci_get_pstate_id(power_state))
|
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|
|
|
return PSCI_E_INVALID_PARAMS;
|
|
|
|
|
|
|
|
|
|
return PSCI_E_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void mtk_system_pwr_domain_resume(void)
|
|
|
|
|
{
|
|
|
|
|
console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
|
|
|
|
|
|
|
|
|
|
/* Assert system power domain is available on the platform */
|
|
|
|
|
assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2);
|
|
|
|
|
|
|
|
|
|
arm_gic_cpuif_setup();
|
|
|
|
|
arm_gic_pcpu_distif_setup();
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if ENABLE_PLAT_COMPAT
|
|
|
|
|
/*******************************************************************************
|
|
|
|
|
* Export the platform handlers to enable psci to invoke them
|
|
|
|
|
******************************************************************************/
|
|
|
|
@ -524,3 +765,54 @@ int platform_setup_pm(const plat_pm_ops_t **plat_ops)
|
|
|
|
|
*plat_ops = &plat_plat_pm_ops;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
static const plat_psci_ops_t plat_plat_pm_ops = {
|
|
|
|
|
.cpu_standby = plat_cpu_standby,
|
|
|
|
|
.pwr_domain_on = plat_power_domain_on,
|
|
|
|
|
.pwr_domain_on_finish = plat_power_domain_on_finish,
|
|
|
|
|
.pwr_domain_off = plat_power_domain_off,
|
|
|
|
|
.pwr_domain_suspend = plat_power_domain_suspend,
|
|
|
|
|
.pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
|
|
|
|
|
.system_off = plat_system_off,
|
|
|
|
|
.system_reset = plat_system_reset,
|
|
|
|
|
.validate_power_state = plat_validate_power_state,
|
|
|
|
|
.get_sys_suspend_power_state = plat_get_sys_suspend_power_state,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
|
|
|
|
const plat_psci_ops_t **psci_ops)
|
|
|
|
|
{
|
|
|
|
|
*psci_ops = &plat_plat_pm_ops;
|
|
|
|
|
secure_entrypoint = sec_entrypoint;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The PSCI generic code uses this API to let the platform participate in state
|
|
|
|
|
* coordination during a power management operation. It compares the platform
|
|
|
|
|
* specific local power states requested by each cpu for a given power domain
|
|
|
|
|
* and returns the coordinated target power state that the domain should
|
|
|
|
|
* enter. A platform assigns a number to a local power state. This default
|
|
|
|
|
* implementation assumes that the platform assigns these numbers in order of
|
|
|
|
|
* increasing depth of the power state i.e. for two power states X & Y, if X < Y
|
|
|
|
|
* then X represents a shallower power state than Y. As a result, the
|
|
|
|
|
* coordinated target local power state for a power domain will be the minimum
|
|
|
|
|
* of the requested local power states.
|
|
|
|
|
*/
|
|
|
|
|
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
|
|
|
|
|
const plat_local_state_t *states,
|
|
|
|
|
unsigned int ncpu)
|
|
|
|
|
{
|
|
|
|
|
plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
|
|
|
|
|
|
|
|
|
|
assert(ncpu);
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
temp = *states++;
|
|
|
|
|
if (temp < target)
|
|
|
|
|
target = temp;
|
|
|
|
|
} while (--ncpu);
|
|
|
|
|
|
|
|
|
|
return target;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|