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feat(trbe): initialize trap settings of trace buffer control registers access 

Trap bits of trace buffer control registers access are in
architecturally UNKNOWN state at boot hence

1. Initialized these bits to zero to prohibit trace buffer control
   registers accesses in lower ELs (EL2, EL1) in all security states
   when FEAT_TRBE is implemented
2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and
   hence setting it to zero also aligns with the Arm ARM reference
   recommendation, that mentions software must writes RES0 bits with
   all 0s

Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
This commit is contained in:
Manish V Badarkhe 2021-06-23 20:02:39 +01:00
parent abd63ed0c5
commit 40ff907470
3 changed files with 20 additions and 2 deletions
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5
include/arch/aarch64/arch.h
View File

@ -442,6 +442,9 @@
#define MDCR_EnPMSN_BIT (ULL(1) << 36)
#define MDCR_MPMX_BIT (ULL(1) << 35)
#define MDCR_MCCD_BIT (ULL(1) << 34)
#define MDCR_NSTB(x) ((x) << 24)
#define MDCR_NSTB_EL1 ULL(0x3)
#define MDCR_NSTBE (ULL(1) << 26)
#define MDCR_MTPME_BIT (ULL(1) << 28)
#define MDCR_TDCC_BIT (ULL(1) << 27)
#define MDCR_SCCD_BIT (ULL(1) << 23)
@ -465,6 +468,8 @@
/* MDCR_EL2 definitions */
#define MDCR_EL2_MTPME (U(1) << 28)
#define MDCR_EL2_HLP (U(1) << 26)
#define MDCR_EL2_E2TB(x) ((x) << 24)
#define MDCR_EL2_E2TB_EL1 U(0x3)
#define MDCR_EL2_HCCD (U(1) << 23)
#define MDCR_EL2_TTRF (U(1) << 19)
#define MDCR_EL2_HPMD (U(1) << 17)

9
include/arch/aarch64/el3_common_macros.S
View File

@ -126,12 +126,19 @@
* Debug is not implemented this bit does not have any effect on the
* counters unless there is support for the implementation defined
* authentication interface ExternalSecureNoninvasiveDebugEnabled().
*
* MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer
* owning security state is Secure state. If FEAT_TRBE is implemented,
* accesses to Trace Buffer control registers at EL2 and EL1 in any
* security state generates trap exceptions to EL3.
* If FEAT_TRBE is not implemented, these bits are RES0.
* ---------------------------------------------------------------------
*/
mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
MDCR_TDA_BIT | MDCR_TPM_BIT))
MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \
MDCR_NSTBE))
msr mdcr_el3, x0

8
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -565,6 +565,11 @@ void cm_prepare_el3_exit(uint32_t security_state)
*
* MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
* architecturally-defined reset value.
*
* MDCR_EL2.E2TB: Set to zero so that the trace Buffer
* owning exception level is NS-EL1 and, tracing is
* prohibited at NS-EL2. These bits are RES0 when
* FEAT_TRBE is not implemented.
*/
mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
MDCR_EL2_HPMD) |
@ -574,7 +579,8 @@ void cm_prepare_el3_exit(uint32_t security_state)
MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
MDCR_EL2_TPMCR_BIT);
MDCR_EL2_TPMCR_BIT |
MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
write_mdcr_el2(mdcr_el2);