40ff907470
Trap bits of trace buffer control registers access are in architecturally UNKNOWN state at boot hence 1. Initialized these bits to zero to prohibit trace buffer control registers accesses in lower ELs (EL2, EL1) in all security states when FEAT_TRBE is implemented 2. Also, these bits are RES0 when FEAT_TRBE is not implemented, and hence setting it to zero also aligns with the Arm ARM reference recommendation, that mentions software must writes RES0 bits with all 0s Change-Id: If2752fd314881219f232f21d8e172a9c6d341ea1 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> |
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readme.rst
Trusted Firmware-A
Trusted Firmware-A (TF-A) is a reference implementation of secure world software for Arm A-Profile architectures (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) Secure Monitor. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states.
TF-A implements Arm interface standards, including:
- Power State Coordination Interface (PSCI)
- Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)
- SMC Calling Convention
- System Control and Management Interface (SCMI)
- Software Delegated Exception Interface (SDEI)
The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures.
In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology.
Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A.
More Info and Documentation
To find out more about Trusted Firmware-A, please view the full documentation that is available through trustedfirmware.org.
Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.