feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces TARGET_PLATFORM variable to account for the differences between TC0 and TC1. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
This commit is contained in:
Usama Arif
parent
8ce073e420
commit
6ec0c65b09
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@ -415,13 +415,13 @@ Arm Reference Design platform ports
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:|F|: plat/arm/board/rdv1mc/
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:|F|: plat/arm/board/sgi575/
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Arm Total Compute(tc0) platform port
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Arm Total Compute platform port
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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:|M|: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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:|G|: `arugan02`_
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:|M|: Usama Arif <usama.arif@arm.com>
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:|G|: `uarif1`_
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:|F|: plat/arm/board/tc0
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:|F|: plat/arm/board/tc
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HiSilicon HiKey and HiKey960 platform ports
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -8,7 +8,7 @@ Arm Development Platforms
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juno/index
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fvp/index
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fvp-ve/index
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tc0/index
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tc/index
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arm_fpga/index
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arm-build-options
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morello/index
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@ -1,7 +1,7 @@
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TC0 Total Compute Platform
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TC Total Compute Platform
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==========================
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Some of the features of TC0 platform referenced in TF-A include:
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Some of the features of TC platform referenced in TF-A include:
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- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
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to abstract power and system management tasks away from application
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@ -13,6 +13,12 @@ Some of the features of TC0 platform referenced in TF-A include:
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- SCMI
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- MHUv2
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Currently, the main difference between TC0 (TARGET_PLATFORM=0) and TC1
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(TARGET_PLATFORM=1) platforms w.r.t to TF-A is the CPUs supported. TC0 has
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support for Cortex A510, Cortex A710 and Cortex X2, while TC1 has support for
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Cortex A510, Cortex Makalu and Cortex Makalu ELP Arm CPUs.
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Boot Sequence
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-------------
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@ -34,8 +40,8 @@ Build Procedure (TF-A only)
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.. code:: shell
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make PLAT=tc0 BL33=<path_to_uboot.bin> \
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SCP_BL2=<path_to_scp_ramfw.bin> all fip
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make PLAT=tc BL33=<path_to_uboot.bin> \
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SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1} all fip
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Enable TBBR by adding the following options to the make command:
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@ -47,4 +53,4 @@ Build Procedure (TF-A only)
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ARM_ROTPK_LOCATION=devel_rsa \
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ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
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*Copyright (c) 2020, Arm Limited. All rights reserved.*
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*Copyright (c) 2020-2021, Arm Limited. All rights reserved.*
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@ -7,7 +7,7 @@
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/dts-v1/;
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/ {
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compatible = "arm,tc0";
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compatible = "arm,tc";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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@ -110,7 +110,7 @@
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};
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};
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/* 32MB of TC0_TZC_DRAM1_BASE */
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/* 32MB of TC_TZC_DRAM1_BASE */
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memory@fd000000 {
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device_type = "memory";
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reg = <0x0 0xfd000000 0x2000000>;
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@ -116,7 +116,7 @@
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};
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};
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/* 32MB of TC0_TZC_DRAM1_BASE */
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/* 32MB of TC_TZC_DRAM1_BASE */
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memory@fd000000 {
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device_type = "memory";
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reg = <0x0 0xfd000000 0x2000000>;
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@ -29,38 +29,38 @@
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* - BL32_BASE when SPD_spmd is enabled
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* - Region to load Trusted OS
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*/
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#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
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TC0_TZC_DRAM1_SIZE)
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#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
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#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \
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TC0_TZC_DRAM1_SIZE - 1)
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#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
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TC_TZC_DRAM1_SIZE)
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#define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
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#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
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TC_TZC_DRAM1_SIZE - 1)
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#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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#define TC_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE - \
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TC0_TZC_DRAM1_SIZE)
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#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \
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TC0_NS_DRAM1_SIZE - 1)
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TC_TZC_DRAM1_SIZE)
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#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \
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TC_NS_DRAM1_SIZE - 1)
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/*
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* Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure)
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* Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
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*/
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#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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TC0_NS_DRAM1_BASE, \
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TC0_NS_DRAM1_SIZE, \
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#define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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TC_NS_DRAM1_BASE, \
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TC_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
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TC0_TZC_DRAM1_BASE, \
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TC0_TZC_DRAM1_SIZE, \
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#define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
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TC_TZC_DRAM1_BASE, \
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TC_TZC_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to
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* Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to
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* max size of BL32 image.
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*/
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#if defined(SPD_spmd)
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#define PLAT_ARM_SPMC_BASE TC0_TZC_DRAM1_BASE
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#define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE
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#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
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#endif
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@ -152,18 +152,18 @@
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#endif
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#define TC0_DEVICE_BASE 0x21000000
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#define TC0_DEVICE_SIZE 0x5f000000
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#define TC_DEVICE_BASE 0x21000000
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#define TC_DEVICE_SIZE 0x5f000000
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// TC0_MAP_DEVICE covers different peripherals
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// TC_MAP_DEVICE covers different peripherals
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// available to the platform
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#define TC0_MAP_DEVICE MAP_REGION_FLAT( \
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TC0_DEVICE_BASE, \
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TC0_DEVICE_SIZE, \
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#define TC_MAP_DEVICE MAP_REGION_FLAT( \
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TC_DEVICE_BASE, \
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TC_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define TC0_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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@ -250,14 +250,14 @@
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
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/*
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* The first region below, TC0_TZC_DRAM1_BASE (0xfd000000) to
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* The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to
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* ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as
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* secure. The second region gives non secure access to rest of DRAM.
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*/
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#define TC0_TZC_REGIONS_DEF \
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{TC0_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
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#define TC_TZC_REGIONS_DEF \
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{TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
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TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
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{TC0_NS_DRAM1_BASE, TC0_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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{TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
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PLAT_ARM_TZC_NS_DEV_ACCESS}
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/* virtual address used by dynamic mem_protect for chunk_base */
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@ -15,7 +15,7 @@
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/* ---------------------------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Function to calculate the core position on TC0.
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* Function to calculate the core position on TC.
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*
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* (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
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* (CPUId * PLAT_MAX_PE_PER_CPU) +
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@ -0,0 +1,12 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TC_PLAT_H
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#define TC_PLAT_H
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void tc_bl31_common_platform_setup(void);
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#endif /* TC_PLAT_H */
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@ -1,8 +1,12 @@
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# Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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# Copyright (c) 2021, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq ($(filter ${TARGET_PLATFORM}, 0 1),)
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$(error TARGET_PLATFORM must be 0 or 1)
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endif
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CSS_LOAD_SCP_IMAGES := 1
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CSS_USE_SCMI_SDS_DRIVER := 1
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@ -39,46 +43,57 @@ override NEED_BL2U := no
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override ARM_PLAT_MT := 1
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TC0_BASE = plat/arm/board/tc0
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TC_BASE = plat/arm/board/tc
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PLAT_INCLUDES += -I${TC0_BASE}/include/
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PLAT_INCLUDES += -I${TC_BASE}/include/
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TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S \
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lib/cpus/aarch64/cortex_a710.S \
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# Common CPU libraries
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TC_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S
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# CPU libraries for TARGET_PLATFORM=0
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ifeq (${TARGET_PLATFORM}, 0)
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TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a710.S \
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lib/cpus/aarch64/cortex_x2.S
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endif
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INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c
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# CPU libraries for TARGET_PLATFORM=1
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ifeq (${TARGET_PLATFORM}, 1)
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TC_CPU_SOURCES += lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu_elp_arm.S
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endif
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PLAT_BL_COMMON_SOURCES += ${TC0_BASE}/tc0_plat.c \
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${TC0_BASE}/include/tc0_helpers.S
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INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c
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PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \
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${TC_BASE}/include/tc_helpers.S
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BL1_SOURCES += ${INTERCONNECT_SOURCES} \
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${TC0_CPU_SOURCES} \
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${TC0_BASE}/tc0_trusted_boot.c \
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${TC0_BASE}/tc0_err.c \
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${TC_CPU_SOURCES} \
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${TC_BASE}/tc_trusted_boot.c \
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${TC_BASE}/tc_err.c \
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drivers/arm/sbsa/sbsa.c
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BL2_SOURCES += ${TC0_BASE}/tc0_security.c \
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${TC0_BASE}/tc0_err.c \
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${TC0_BASE}/tc0_trusted_boot.c \
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BL2_SOURCES += ${TC_BASE}/tc_security.c \
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${TC_BASE}/tc_err.c \
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${TC_BASE}/tc_trusted_boot.c \
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lib/utils/mem_region.c \
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drivers/arm/tzc/tzc400.c \
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plat/arm/common/arm_tzc400.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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BL31_SOURCES += ${INTERCONNECT_SOURCES} \
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${TC0_CPU_SOURCES} \
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${TC_CPU_SOURCES} \
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${ENT_GIC_SOURCES} \
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${TC0_BASE}/tc0_bl31_setup.c \
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${TC0_BASE}/tc0_topology.c \
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${TC_BASE}/tc_bl31_setup.c \
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${TC_BASE}/tc_topology.c \
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drivers/cfi/v2m/v2m_flash.c \
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lib/utils/mem_region.c \
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plat/arm/common/arm_nor_psci_mem_protect.c
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# Add the FDT_SOURCES and options for Dynamic Config
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FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_fw_config.dts \
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${TC0_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \
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${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts
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FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
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TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
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@ -89,24 +104,24 @@ $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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ifeq (${SPD},spmd)
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ifeq ($(ARM_SPMC_MANIFEST_DTS),)
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ARM_SPMC_MANIFEST_DTS := ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts
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ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts
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endif
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FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
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TC0_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
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TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
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# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG}))
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$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG}))
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endif
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#Device tree
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TC0_HW_CONFIG_DTS := fdts/tc0.dts
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TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
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FDT_SOURCES += ${TC0_HW_CONFIG_DTS}
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$(eval TC0_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC0_HW_CONFIG_DTS)))
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TC_HW_CONFIG_DTS := fdts/tc.dts
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TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
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FDT_SOURCES += ${TC_HW_CONFIG_DTS}
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$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS)))
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# Add the HW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TC0_HW_CONFIG},--hw-config,${TC0_HW_CONFIG}))
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$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG}))
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override CTX_INCLUDE_AARCH32_REGS := 0
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@ -7,7 +7,7 @@
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#include <assert.h>
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#include <libfdt.h>
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#include <tc0_plat.h>
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#include <tc_plat.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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@ -16,7 +16,7 @@
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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static scmi_channel_plat_info_t tc0_scmi_plat_info[] = {
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static scmi_channel_plat_info_t tc_scmi_plat_info[] = {
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{
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.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
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.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
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@ -28,13 +28,13 @@ static scmi_channel_plat_info_t tc0_scmi_plat_info[] = {
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void bl31_platform_setup(void)
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{
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tc0_bl31_common_platform_setup();
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tc_bl31_common_platform_setup();
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}
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scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
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{
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return &tc0_scmi_plat_info[channel_id];
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return &tc_scmi_plat_info[channel_id];
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}
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@ -44,7 +44,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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}
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void tc0_bl31_common_platform_setup(void)
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void tc_bl31_common_platform_setup(void)
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{
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arm_bl31_platform_setup();
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}
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|
|
@ -7,7 +7,7 @@
|
|||
#include <plat/arm/common/plat_arm.h>
|
||||
|
||||
/*
|
||||
* tc0 error handler
|
||||
* tc error handler
|
||||
*/
|
||||
void __dead2 plat_arm_error_handler(int err)
|
||||
{
|
||||
|
|
@ -28,19 +28,19 @@
|
|||
#if IMAGE_BL1
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
TC0_FLASH0_RO,
|
||||
TC0_MAP_DEVICE,
|
||||
TC_FLASH0_RO,
|
||||
TC_MAP_DEVICE,
|
||||
{0}
|
||||
};
|
||||
#endif
|
||||
#if IMAGE_BL2
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
TC0_FLASH0_RO,
|
||||
TC0_MAP_DEVICE,
|
||||
TC0_MAP_NS_DRAM1,
|
||||
TC_FLASH0_RO,
|
||||
TC_MAP_DEVICE,
|
||||
TC_MAP_NS_DRAM1,
|
||||
#if defined(SPD_spmd)
|
||||
TC0_MAP_TZC_DRAM1,
|
||||
TC_MAP_TZC_DRAM1,
|
||||
#endif
|
||||
#if ARM_BL31_IN_DRAM
|
||||
ARM_MAP_BL31_SEC_DRAM,
|
||||
|
|
@ -62,7 +62,7 @@ const mmap_region_t plat_arm_mmap[] = {
|
|||
const mmap_region_t plat_arm_mmap[] = {
|
||||
ARM_MAP_SHARED_RAM,
|
||||
V2M_MAP_IOFPGA,
|
||||
TC0_MAP_DEVICE,
|
||||
TC_MAP_DEVICE,
|
||||
#if SPM_MM
|
||||
ARM_SPM_BUF_EL3_MMAP,
|
||||
#endif
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
#include <platform_def.h>
|
||||
|
||||
static const arm_tzc_regions_info_t tzc_regions[] = {
|
||||
TC0_TZC_REGIONS_DEF,
|
||||
TC_TZC_REGIONS_DEF,
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
/******************************************************************************
|
||||
* The power domain tree descriptor.
|
||||
******************************************************************************/
|
||||
const unsigned char tc0_pd_tree_desc[] = {
|
||||
const unsigned char tc_pd_tree_desc[] = {
|
||||
PLAT_ARM_CLUSTER_COUNT,
|
||||
PLAT_MAX_CPUS_PER_CLUSTER,
|
||||
};
|
||||
|
|
@ -20,7 +20,7 @@ const unsigned char tc0_pd_tree_desc[] = {
|
|||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return tc0_pd_tree_desc;
|
||||
return tc_pd_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef tc0_bl31_common_platform_setup_PLAT_H
|
||||
#define tc0_bl31_common_platform_setup_PLAT_H
|
||||
|
||||
void tc0_bl31_common_platform_setup(void);
|
||||
|
||||
#endif /* tc0_bl31_common_platform_setup_PLAT_H */
|
||||
Loading…
Reference in New Issue