Merge changes from topic "qemu-sbsa-topology-psci" into integration
* changes: qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller qemu/qemu_sbsa: topology is different from qemu so add handling qemu/common : change DEVICE2 definition for MMU qemu/aarch64/plat_helpers.S : calculate the position shift
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
43d97fae9a
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@ -32,7 +32,8 @@ endfunc plat_my_core_pos
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func plat_qemu_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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add x0, x1, x0, LSR #(MPIDR_AFFINITY_BITS -\
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PLATFORM_CPU_PER_CLUSTER_SHIFT)
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ret
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endfunc plat_qemu_calc_core_pos
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@ -26,7 +26,7 @@
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#ifdef DEVICE2_BASE
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#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
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DEVICE2_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
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@ -93,6 +93,9 @@ static const mmap_region_t plat_qemu_mmap[] = {
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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#ifdef MAP_DEVICE2
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MAP_DEVICE2,
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#endif
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#if SPM_MM
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MAP_NS_DRAM0,
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QEMU_SPM_BUF_EL3_MMAP,
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@ -108,6 +111,9 @@ static const mmap_region_t plat_qemu_mmap[] = {
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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#ifdef MAP_DEVICE2
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MAP_DEVICE2,
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#endif
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{0}
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};
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@ -24,6 +24,14 @@
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#else
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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/*
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* Define the number of cores per cluster used in calculating core position.
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* The cluster number is shifted by this value and added to the core ID,
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* so its value represents log2(cores/cluster).
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* Default is 2**(2) = 4 cores per cluster.
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*/
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#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(2)
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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@ -16,13 +16,17 @@
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#define PLATFORM_STACK_SIZE 0x1000
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
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PLATFORM_CLUSTER1_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
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/*
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* Define the number of cores per cluster used in calculating core position.
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* The cluster number is shifted by this value and added to the core ID,
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* so its value represents log2(cores/cluster).
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* Default is 2**(3) = 8 cores per cluster.
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*/
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#define PLATFORM_CPU_PER_CLUSTER_SHIFT U(3)
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#define PLATFORM_CLUSTER_COUNT U(64)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define QEMU_PRIMARY_CPU U(0)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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@ -130,7 +134,7 @@
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_SIZE 0x50000
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#define BL31_SIZE 0x300000
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#define BL31_BASE (BL31_LIMIT - BL31_SIZE)
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#define BL31_LIMIT (BL1_RW_BASE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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@ -157,10 +161,10 @@
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42)
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#if SPM_MM
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#define MAX_MMAP_REGIONS 12
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#define MAX_XLAT_TABLES 11
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#define MAX_XLAT_TABLES 12
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#else
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#define MAX_MMAP_REGIONS 11
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#define MAX_XLAT_TABLES 10
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#define MAX_XLAT_TABLES 11
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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@ -203,7 +207,10 @@
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#define DEVICE0_SIZE 0x04080000
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/* This is map from NORMAL_UART up to SECURE_UART_MM */
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#define DEVICE1_BASE 0x60000000
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#define DEVICE1_SIZE 0x00041000
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#define DEVICE1_SIZE 0x10041000
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/* This is a map for SECURE_EC */
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#define DEVICE2_BASE 0x50000000
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#define DEVICE2_SIZE 0x00001000
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/*
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* GIC related constants
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@ -79,8 +79,8 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \
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lib/semihosting/semihosting.c \
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lib/semihosting/${ARCH}/semihosting_call.S \
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plat/common/plat_psci_common.c \
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${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
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${PLAT_QEMU_COMMON_PATH}/topology.c \
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${PLAT_QEMU_PATH}/sbsa_pm.c \
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${PLAT_QEMU_PATH}/sbsa_topology.c \
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${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
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common/fdt_fixup.c \
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@ -0,0 +1,237 @@
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/*
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* Copyright (c) 2020, Nuvia Inc
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "sbsa_private.h"
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#define ADP_STOPPED_APPLICATION_EXIT 0x20026
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/*
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* Define offset and commands for the fake EC device
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*/
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#define SBSA_SECURE_EC_OFFSET 0x50000000
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#define SBSA_SECURE_EC_CMD_SHUTDOWN 0x01
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#define SBSA_SECURE_EC_CMD_REBOOT 0x02
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/*
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* The secure entry point to be used on warm reset.
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*/
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static unsigned long secure_entrypoint;
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/* Make composite power state parameter till power level 0 */
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#if PSCI_EXTENDED_STATE_ID
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#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#else
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#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#endif /* PSCI_EXTENDED_STATE_ID */
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#define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \
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qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/*
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* The table storing the valid idle power states. Ensure that the
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* array entries are populated in ascending order of state-id to
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* enable us to use binary search during power state validation.
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* The table must be terminated by a NULL entry.
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*/
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static const unsigned int qemu_pm_idle_states[] = {
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/* State-id - 0x01 */
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qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET,
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MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x02 */
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qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF,
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MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x22 */
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qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF,
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MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN),
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0
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};
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/*******************************************************************************
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* Platform handler called to check the validity of the power state
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* parameter. The power state parameter has to be a composite power state.
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******************************************************************************/
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static int qemu_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int state_id;
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unsigned int i;
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assert(req_state != NULL);
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/*
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* Currently we are using a linear search for finding the matching
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* entry in the idle power state array. This can be made a binary
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* search if the number of entries justifies the additional complexity.
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*/
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for (i = 0U; qemu_pm_idle_states[i] != 0U; i++) {
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if (power_state == qemu_pm_idle_states[i]) {
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break;
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}
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}
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/* Return error if entry not found in the idle state array */
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if (qemu_pm_idle_states[i] == 0U) {
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return PSCI_E_INVALID_PARAMS;
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}
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i = 0U;
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state_id = psci_get_pstate_id(power_state);
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/* Parse the State ID and populate the state info parameter */
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while (state_id != 0U) {
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req_state->pwr_domain_state[i++] = state_id &
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PLAT_LOCAL_PSTATE_MASK;
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state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler called when a CPU is about to enter standby.
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******************************************************************************/
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static void qemu_cpu_standby(plat_local_state_t cpu_state)
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{
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assert(cpu_state == PLAT_LOCAL_STATE_RET);
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/*
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* Enter standby state
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* dsb is good practice before using wfi to enter low power states
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*/
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dsb();
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wfi();
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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static int qemu_pwr_domain_on(u_register_t mpidr)
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{
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int pos = plat_core_pos_by_mpidr(mpidr);
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uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE;
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if (pos < 0) {
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return PSCI_E_INVALID_PARAMS;
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}
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hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO;
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dsb();
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sev();
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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static void qemu_pwr_domain_off(const psci_power_state_t *target_state)
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{
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qemu_pwr_gic_off();
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}
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void __dead2 plat_secondary_cold_boot_setup(void);
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static void __dead2
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qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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disable_mmu_el3();
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plat_secondary_cold_boot_setup();
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}
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/*******************************************************************************
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* Platform handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void qemu_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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assert(false);
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}
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/*******************************************************************************
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* Platform handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
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PLAT_LOCAL_STATE_OFF);
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qemu_pwr_gic_on_finish();
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}
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/*******************************************************************************
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* Platform handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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******************************************************************************/
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void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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assert(false);
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}
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/*******************************************************************************
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* Platform handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 qemu_system_off(void)
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{
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mmio_write_32(SBSA_SECURE_EC_OFFSET, SBSA_SECURE_EC_CMD_SHUTDOWN);
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panic();
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}
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static void __dead2 qemu_system_reset(void)
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{
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mmio_write_32(SBSA_SECURE_EC_OFFSET, SBSA_SECURE_EC_CMD_REBOOT);
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panic();
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}
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static const plat_psci_ops_t plat_qemu_psci_pm_ops = {
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.cpu_standby = qemu_cpu_standby,
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.pwr_domain_on = qemu_pwr_domain_on,
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.pwr_domain_off = qemu_pwr_domain_off,
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.pwr_domain_pwr_down_wfi = qemu_pwr_domain_pwr_down_wfi,
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.pwr_domain_suspend = qemu_pwr_domain_suspend,
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.pwr_domain_on_finish = qemu_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish,
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.system_off = qemu_system_off,
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.system_reset = qemu_system_reset,
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.validate_power_state = qemu_validate_power_state
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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uintptr_t *mailbox = (uintptr_t *)PLAT_QEMU_TRUSTED_MAILBOX_BASE;
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*mailbox = sec_entrypoint;
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secure_entrypoint = (unsigned long)sec_entrypoint;
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*psci_ops = &plat_qemu_psci_pm_ops;
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return 0;
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}
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|
|
@ -0,0 +1,17 @@
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/*
|
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* Copyright (c) 2020, Nuvia Inc
|
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*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
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|
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#ifndef SBSA_PRIVATE_H
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#define SBSA_PRIVATE_H
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#include <stdint.h>
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|
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unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
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|
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void qemu_pwr_gic_on_finish(void);
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void qemu_pwr_gic_off(void);
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#endif /* SBSA_PRIVATE_H */
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|
|
@ -0,0 +1,63 @@
|
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/*
|
||||
* Copyright (c) 2020, Nuvia Inc
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
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#include <common/debug.h>
|
||||
|
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#include <platform_def.h>
|
||||
#include "sbsa_private.h"
|
||||
|
||||
/* The power domain tree descriptor */
|
||||
static unsigned char power_domain_tree_desc[PLATFORM_CLUSTER_COUNT + 1];
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the sbsa-ref default topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
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{
|
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unsigned int i;
|
||||
|
||||
power_domain_tree_desc[0] = PLATFORM_CLUSTER_COUNT;
|
||||
|
||||
for (i = 0U; i < PLATFORM_CLUSTER_COUNT; i++) {
|
||||
power_domain_tree_desc[i + 1] = PLATFORM_MAX_CPUS_PER_CLUSTER;
|
||||
}
|
||||
|
||||
return power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements a part of the critical interface between the psci
|
||||
* generic layer and the platform that allows the former to query the platform
|
||||
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
||||
* in case the MPIDR is invalid.
|
||||
******************************************************************************/
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int cluster_id, cpu_id;
|
||||
|
||||
mpidr &= MPIDR_AFFINITY_MASK;
|
||||
if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) {
|
||||
ERROR("Invalid MPIDR\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
|
||||
if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
|
||||
ERROR("cluster_id >= PLATFORM_CLUSTER_COUNT define\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
|
||||
ERROR("cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER define\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return plat_qemu_calc_core_pos(mpidr);
|
||||
}
|
||||
Loading…
Reference in New Issue