Merge pull request #1845 from ambroise-arm/av/errata
Apply workarounds for errata of Cortex-A53, A55 and A57
This commit is contained in:
commit
4476838ae8
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@ -73,9 +73,18 @@ will enable it.
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For Cortex-A53, the following errata build flags are defined :
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For Cortex-A53, the following errata build flags are defined :
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- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
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CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
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- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
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CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
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- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
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- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
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CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
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CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
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- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
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CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
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- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
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- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
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link time to Cortex-A53 CPU. This needs to be enabled for some variants of
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link time to Cortex-A53 CPU. This needs to be enabled for some variants of
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revision <= r0p4. This workaround can lead the linker to create ``*.stub``
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revision <= r0p4. This workaround can lead the linker to create ``*.stub``
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@ -97,6 +106,23 @@ For Cortex-A53, the following errata build flags are defined :
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Earlier revisions of the CPU have other errata which require the same
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Earlier revisions of the CPU have other errata which require the same
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workaround in software, so they should be covered anyway.
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workaround in software, so they should be covered anyway.
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For Cortex-A55, the following errata build flags are defined :
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- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
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CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
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- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
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CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
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For Cortex-A57, the following errata build flags are defined :
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For Cortex-A57, the following errata build flags are defined :
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- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
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- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
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@ -108,6 +134,12 @@ For Cortex-A57, the following errata build flags are defined :
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- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
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- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
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- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
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- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
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@ -71,7 +71,11 @@
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/* Data Cache set/way op type defines */
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/* Data Cache set/way op type defines */
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#define DC_OP_ISW U(0x0)
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#define DC_OP_ISW U(0x0)
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#define DC_OP_CISW U(0x1)
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#define DC_OP_CISW U(0x1)
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#if ERRATA_A53_827319
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#define DC_OP_CSW DC_OP_CISW
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#else
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#define DC_OP_CSW U(0x2)
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#define DC_OP_CSW U(0x2)
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#endif
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/*******************************************************************************
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets
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* Generic timer memory mapped registers & offsets
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@ -328,7 +328,11 @@ DEFINE_BPIOP_FUNC(allis, BPIALLIS)
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*/
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*/
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DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
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DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
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DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
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DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC)
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#else
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DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
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DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
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#endif
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/* Previously defined accessor functions with incomplete register names */
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/* Previously defined accessor functions with incomplete register names */
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#define dsb() dsbsy()
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#define dsb() dsbsy()
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@ -119,7 +119,11 @@
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/* Data cache set/way op type defines */
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/* Data cache set/way op type defines */
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#define DCISW U(0x0)
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#define DCISW U(0x0)
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#define DCCISW U(0x1)
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#define DCCISW U(0x1)
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#if ERRATA_A53_827319
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#define DCCSW DCCISW
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#else
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#define DCCSW U(0x2)
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#define DCCSW U(0x2)
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#endif
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/* ID_AA64PFR0_EL1 definitions */
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/* ID_AA64PFR0_EL1 definitions */
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#define ID_AA64PFR0_EL0_SHIFT U(0)
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#define ID_AA64PFR0_EL0_SHIFT U(0)
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@ -113,6 +113,18 @@ static inline void tlbi ## _type(uint64_t v) \
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}
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}
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#endif /* ERRATA_A57_813419 */
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#endif /* ERRATA_A57_813419 */
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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/*
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* Define function for DC instruction with register parameter that enables
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* the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
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*/
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#define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
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static inline void dc ## _name(uint64_t v) \
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{ \
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__asm__("dc " #_type ", %0" : : "r" (v)); \
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}
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#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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@ -143,11 +155,23 @@ DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
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******************************************************************************/
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******************************************************************************/
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
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#if ERRATA_A53_827319
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DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
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#endif
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
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#endif
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
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#endif
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
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/*******************************************************************************
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/*******************************************************************************
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@ -45,6 +45,7 @@
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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@ -18,6 +18,24 @@
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#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24)
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49)
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/*******************************************************************************
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* CPU Identification register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1
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#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6)
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/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
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/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
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#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
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#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
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@ -45,6 +45,7 @@
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#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -29,6 +29,36 @@ func cortex_a53_disable_smp
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bx lr
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bx lr
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endfunc cortex_a53_disable_smp
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endfunc cortex_a53_disable_smp
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #819472.
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* This applies only to revision <= r0p1 of Cortex A53.
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* ---------------------------------------------------
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*/
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func check_errata_819472
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/*
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* Even though this is only needed for revision <= r0p1, it
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* is always applied due to limitations of the current
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* errata framework.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_819472
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #824069.
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* This applies only to revision <= r0p2 of Cortex A53.
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* ---------------------------------------------------
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*/
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func check_errata_824069
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/*
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* Even though this is only needed for revision <= r0p2, it
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* is always applied due to limitations of the current
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* errata framework.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_824069
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/* --------------------------------------------------
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #826319.
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* Errata Workaround for Cortex A53 Errata #826319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* This applies only to revision <= r0p2 of Cortex A53.
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@ -59,6 +89,21 @@ func check_errata_826319
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b cpu_rev_var_ls
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b cpu_rev_var_ls
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endfunc check_errata_826319
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endfunc check_errata_826319
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #827319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* ---------------------------------------------------
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*/
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func check_errata_827319
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/*
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* Even though this is only needed for revision <= r0p2, it
|
||||||
|
* is always applied due to limitations of the current
|
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* errata framework.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_827319
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/* ---------------------------------------------------------------------
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/* ---------------------------------------------------------------------
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* Disable the cache non-temporal hint.
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* Disable the cache non-temporal hint.
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*
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*
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@ -253,7 +298,10 @@ func cortex_a53_errata_report
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* Report all errata. The revision-variant information is passed to
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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* checking functions of each errata.
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*/
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*/
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report_errata ERRATA_A53_819472, cortex_a53, 819472
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report_errata ERRATA_A53_824069, cortex_a53, 824069
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_827319, cortex_a53, 827319
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report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
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report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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@ -1,5 +1,5 @@
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||||||
/*
|
/*
|
||||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*/
|
*/
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||||||
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@ -46,6 +46,13 @@ func cortex_a57_disable_ext_debug
|
||||||
mov r0, #1
|
mov r0, #1
|
||||||
stcopr r0, DBGOSDLR
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stcopr r0, DBGOSDLR
|
||||||
isb
|
isb
|
||||||
|
#if ERRATA_A57_817169
|
||||||
|
/*
|
||||||
|
* Invalidate any TLB address
|
||||||
|
*/
|
||||||
|
mov r0, #0
|
||||||
|
stcopr r0, TLBIMVA
|
||||||
|
#endif
|
||||||
dsb sy
|
dsb sy
|
||||||
bx lr
|
bx lr
|
||||||
endfunc cortex_a57_disable_ext_debug
|
endfunc cortex_a57_disable_ext_debug
|
||||||
|
@ -123,6 +130,49 @@ func check_errata_813420
|
||||||
b cpu_rev_var_ls
|
b cpu_rev_var_ls
|
||||||
endfunc check_errata_813420
|
endfunc check_errata_813420
|
||||||
|
|
||||||
|
/* ---------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A57 Errata #814670.
|
||||||
|
* This applies only to revision r0p0 of Cortex A57.
|
||||||
|
* Inputs:
|
||||||
|
* r0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: r0-r3
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a57_814670_wa
|
||||||
|
/*
|
||||||
|
* Compare r0 against revision r0p0
|
||||||
|
*/
|
||||||
|
mov r2, lr
|
||||||
|
bl check_errata_814670
|
||||||
|
cmp r0, #ERRATA_NOT_APPLIES
|
||||||
|
beq 1f
|
||||||
|
ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||||
|
orr64_imm r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION
|
||||||
|
stcopr16 r0, r1, CORTEX_A57_CPUACTLR
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
bx r2
|
||||||
|
endfunc errata_a57_814670_wa
|
||||||
|
|
||||||
|
func check_errata_814670
|
||||||
|
mov r1, #0x00
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_814670
|
||||||
|
|
||||||
|
/* ----------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A57 Errata #817169.
|
||||||
|
* This applies only to revision <= r0p1 of Cortex A57.
|
||||||
|
* ----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func check_errata_817169
|
||||||
|
/*
|
||||||
|
* Even though this is only needed for revision <= r0p1, it
|
||||||
|
* is always applied because of the low cost of the workaround.
|
||||||
|
*/
|
||||||
|
mov r0, #ERRATA_APPLIES
|
||||||
|
bx lr
|
||||||
|
endfunc check_errata_817169
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
/* --------------------------------------------------------------------
|
||||||
* Disable the over-read from the LDNP instruction.
|
* Disable the over-read from the LDNP instruction.
|
||||||
*
|
*
|
||||||
|
@ -366,6 +416,11 @@ func cortex_a57_reset_func
|
||||||
bl errata_a57_813420_wa
|
bl errata_a57_813420_wa
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A57_814670
|
||||||
|
mov r0, r4
|
||||||
|
bl errata_a57_814670_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
#if A57_DISABLE_NON_TEMPORAL_HINT
|
#if A57_DISABLE_NON_TEMPORAL_HINT
|
||||||
mov r0, r4
|
mov r0, r4
|
||||||
bl a57_disable_ldnp_overread
|
bl a57_disable_ldnp_overread
|
||||||
|
@ -533,6 +588,8 @@ func cortex_a57_errata_report
|
||||||
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
||||||
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
||||||
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
||||||
|
report_errata ERRATA_A57_814670, cortex_a57, 814670
|
||||||
|
report_errata ERRATA_A57_817169, cortex_a57, 817169
|
||||||
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
||||||
disable_ldnp_overread
|
disable_ldnp_overread
|
||||||
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
|
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*/
|
*/
|
||||||
|
@ -42,6 +42,36 @@ func cortex_a53_disable_smp
|
||||||
ret
|
ret
|
||||||
endfunc cortex_a53_disable_smp
|
endfunc cortex_a53_disable_smp
|
||||||
|
|
||||||
|
/* ---------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A53 Errata #819472.
|
||||||
|
* This applies only to revision <= r0p1 of Cortex A53.
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*/
|
||||||
|
func check_errata_819472
|
||||||
|
/*
|
||||||
|
* Even though this is only needed for revision <= r0p1, it
|
||||||
|
* is always applied due to limitations of the current
|
||||||
|
* errata framework.
|
||||||
|
*/
|
||||||
|
mov x0, #ERRATA_APPLIES
|
||||||
|
ret
|
||||||
|
endfunc check_errata_819472
|
||||||
|
|
||||||
|
/* ---------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A53 Errata #824069.
|
||||||
|
* This applies only to revision <= r0p2 of Cortex A53.
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*/
|
||||||
|
func check_errata_824069
|
||||||
|
/*
|
||||||
|
* Even though this is only needed for revision <= r0p2, it
|
||||||
|
* is always applied due to limitations of the current
|
||||||
|
* errata framework.
|
||||||
|
*/
|
||||||
|
mov x0, #ERRATA_APPLIES
|
||||||
|
ret
|
||||||
|
endfunc check_errata_824069
|
||||||
|
|
||||||
/* --------------------------------------------------
|
/* --------------------------------------------------
|
||||||
* Errata Workaround for Cortex A53 Errata #826319.
|
* Errata Workaround for Cortex A53 Errata #826319.
|
||||||
* This applies only to revision <= r0p2 of Cortex A53.
|
* This applies only to revision <= r0p2 of Cortex A53.
|
||||||
|
@ -70,6 +100,21 @@ func check_errata_826319
|
||||||
b cpu_rev_var_ls
|
b cpu_rev_var_ls
|
||||||
endfunc check_errata_826319
|
endfunc check_errata_826319
|
||||||
|
|
||||||
|
/* ---------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A53 Errata #827319.
|
||||||
|
* This applies only to revision <= r0p2 of Cortex A53.
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*/
|
||||||
|
func check_errata_827319
|
||||||
|
/*
|
||||||
|
* Even though this is only needed for revision <= r0p2, it
|
||||||
|
* is always applied due to limitations of the current
|
||||||
|
* errata framework.
|
||||||
|
*/
|
||||||
|
mov x0, #ERRATA_APPLIES
|
||||||
|
ret
|
||||||
|
endfunc check_errata_827319
|
||||||
|
|
||||||
/* ---------------------------------------------------------------------
|
/* ---------------------------------------------------------------------
|
||||||
* Disable the cache non-temporal hint.
|
* Disable the cache non-temporal hint.
|
||||||
*
|
*
|
||||||
|
@ -304,7 +349,10 @@ func cortex_a53_errata_report
|
||||||
* Report all errata. The revision-variant information is passed to
|
* Report all errata. The revision-variant information is passed to
|
||||||
* checking functions of each errata.
|
* checking functions of each errata.
|
||||||
*/
|
*/
|
||||||
|
report_errata ERRATA_A53_819472, cortex_a53, 819472
|
||||||
|
report_errata ERRATA_A53_824069, cortex_a53, 824069
|
||||||
report_errata ERRATA_A53_826319, cortex_a53, 826319
|
report_errata ERRATA_A53_826319, cortex_a53, 826319
|
||||||
|
report_errata ERRATA_A53_827319, cortex_a53, 827319
|
||||||
report_errata ERRATA_A53_835769, cortex_a53, 835769
|
report_errata ERRATA_A53_835769, cortex_a53, 835769
|
||||||
report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
|
report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
|
||||||
report_errata ERRATA_A53_843419, cortex_a53, 843419
|
report_errata ERRATA_A53_843419, cortex_a53, 843419
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*/
|
*/
|
||||||
|
@ -11,11 +11,200 @@
|
||||||
#include <cpu_macros.S>
|
#include <cpu_macros.S>
|
||||||
#include <plat_macros.S>
|
#include <plat_macros.S>
|
||||||
|
|
||||||
|
/* --------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A55 Errata #768277.
|
||||||
|
* This applies only to revision r0p0 of Cortex A55.
|
||||||
|
* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* --------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a55_768277_wa
|
||||||
|
/*
|
||||||
|
* Compare x0 against revision r0p0
|
||||||
|
*/
|
||||||
|
mov x17, x30
|
||||||
|
bl check_errata_768277
|
||||||
|
cbz x0, 1f
|
||||||
|
mrs x1, CORTEX_A55_CPUACTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
|
||||||
|
msr CORTEX_A55_CPUACTLR_EL1, x1
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
ret x17
|
||||||
|
endfunc errata_a55_768277_wa
|
||||||
|
|
||||||
|
func check_errata_768277
|
||||||
|
mov x1, #0x00
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_768277
|
||||||
|
|
||||||
|
/* ------------------------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A55 Errata #778703.
|
||||||
|
* This applies only to revision r0p0 of Cortex A55 where L2 cache is
|
||||||
|
* not configured.
|
||||||
|
* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* ------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a55_778703_wa
|
||||||
|
/*
|
||||||
|
* Compare x0 against revision r0p0 and check that no private L2 cache
|
||||||
|
* is configured
|
||||||
|
*/
|
||||||
|
mov x17, x30
|
||||||
|
bl check_errata_778703
|
||||||
|
cbz x0, 1f
|
||||||
|
mrs x1, CORTEX_A55_CPUECTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
|
||||||
|
msr CORTEX_A55_CPUECTLR_EL1, x1
|
||||||
|
mrs x1, CORTEX_A55_CPUACTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
|
||||||
|
msr CORTEX_A55_CPUACTLR_EL1, x1
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
ret x17
|
||||||
|
endfunc errata_a55_778703_wa
|
||||||
|
|
||||||
|
func check_errata_778703
|
||||||
|
mov x16, x30
|
||||||
|
mov x1, #0x00
|
||||||
|
bl cpu_rev_var_ls
|
||||||
|
/*
|
||||||
|
* Check that no private L2 cache is configured
|
||||||
|
*/
|
||||||
|
mrs x1, CORTEX_A55_CLIDR_EL1
|
||||||
|
and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3
|
||||||
|
cmp x1, #0
|
||||||
|
mov x2, #ERRATA_NOT_APPLIES
|
||||||
|
csel x0, x0, x2, eq
|
||||||
|
ret x16
|
||||||
|
endfunc check_errata_778703
|
||||||
|
|
||||||
|
/* --------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A55 Errata #798797.
|
||||||
|
* This applies only to revision r0p0 of Cortex A55.
|
||||||
|
* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* --------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a55_798797_wa
|
||||||
|
/*
|
||||||
|
* Compare x0 against revision r0p0
|
||||||
|
*/
|
||||||
|
mov x17, x30
|
||||||
|
bl check_errata_798797
|
||||||
|
cbz x0, 1f
|
||||||
|
mrs x1, CORTEX_A55_CPUACTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
|
||||||
|
msr CORTEX_A55_CPUACTLR_EL1, x1
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
ret x17
|
||||||
|
endfunc errata_a55_798797_wa
|
||||||
|
|
||||||
|
func check_errata_798797
|
||||||
|
mov x1, #0x00
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_798797
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A55 Errata #846532.
|
||||||
|
* This applies only to revisions <= r0p1 of Cortex A55.
|
||||||
|
* Disabling dual-issue has a small impact on performance. Disabling a
|
||||||
|
* power optimization feature is an alternate workaround with no impact
|
||||||
|
* on performance but with an increase in power consumption (see errata
|
||||||
|
* notice).
|
||||||
|
* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* --------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a55_846532_wa
|
||||||
|
/*
|
||||||
|
* Compare x0 against revision r0p1
|
||||||
|
*/
|
||||||
|
mov x17, x30
|
||||||
|
bl check_errata_846532
|
||||||
|
cbz x0, 1f
|
||||||
|
mrs x1, CORTEX_A55_CPUACTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
|
||||||
|
msr CORTEX_A55_CPUACTLR_EL1, x1
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
ret x17
|
||||||
|
endfunc errata_a55_846532_wa
|
||||||
|
|
||||||
|
func check_errata_846532
|
||||||
|
mov x1, #0x01
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_846532
|
||||||
|
|
||||||
|
/* -----------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A55 Errata #903758.
|
||||||
|
* This applies only to revisions <= r0p1 of Cortex A55.
|
||||||
|
* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* -----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a55_903758_wa
|
||||||
|
/*
|
||||||
|
* Compare x0 against revision r0p1
|
||||||
|
*/
|
||||||
|
mov x17, x30
|
||||||
|
bl check_errata_903758
|
||||||
|
cbz x0, 1f
|
||||||
|
mrs x1, CORTEX_A55_CPUACTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
|
||||||
|
msr CORTEX_A55_CPUACTLR_EL1, x1
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
ret x17
|
||||||
|
endfunc errata_a55_903758_wa
|
||||||
|
|
||||||
|
func check_errata_903758
|
||||||
|
mov x1, #0x01
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_903758
|
||||||
|
|
||||||
func cortex_a55_reset_func
|
func cortex_a55_reset_func
|
||||||
mov x19, x30
|
mov x19, x30
|
||||||
|
|
||||||
#if ERRATA_DSU_936184
|
#if ERRATA_DSU_936184
|
||||||
bl errata_dsu_936184_wa
|
bl errata_dsu_936184_wa
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
bl cpu_get_rev_var
|
||||||
|
mov x18, x0
|
||||||
|
|
||||||
|
#if ERRATA_A55_768277
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a55_768277_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A55_778703
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a55_778703_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A55_798797
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a55_798797_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A55_846532
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a55_846532_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A55_903758
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a55_903758_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
ret x19
|
ret x19
|
||||||
endfunc cortex_a55_reset_func
|
endfunc cortex_a55_reset_func
|
||||||
|
|
||||||
|
@ -49,6 +238,11 @@ func cortex_a55_errata_report
|
||||||
* "report_errata" is expecting it and it doesn't corrupt it.
|
* "report_errata" is expecting it and it doesn't corrupt it.
|
||||||
*/
|
*/
|
||||||
report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
|
report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
|
||||||
|
report_errata ERRATA_A55_768277, cortex_a55, 768277
|
||||||
|
report_errata ERRATA_A55_778703, cortex_a55, 778703
|
||||||
|
report_errata ERRATA_A55_798797, cortex_a55, 798797
|
||||||
|
report_errata ERRATA_A55_846532, cortex_a55, 846532
|
||||||
|
report_errata ERRATA_A55_903758, cortex_a55, 903758
|
||||||
|
|
||||||
ldp x8, x30, [sp], #16
|
ldp x8, x30, [sp], #16
|
||||||
ret
|
ret
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
|
* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*/
|
*/
|
||||||
|
@ -59,6 +59,13 @@ func cortex_a57_disable_ext_debug
|
||||||
mov x0, #1
|
mov x0, #1
|
||||||
msr osdlr_el1, x0
|
msr osdlr_el1, x0
|
||||||
isb
|
isb
|
||||||
|
#if ERRATA_A57_817169
|
||||||
|
/*
|
||||||
|
* Invalidate any TLB address
|
||||||
|
*/
|
||||||
|
mov x0, #0
|
||||||
|
tlbi vae3, x0
|
||||||
|
#endif
|
||||||
dsb sy
|
dsb sy
|
||||||
ret
|
ret
|
||||||
endfunc cortex_a57_disable_ext_debug
|
endfunc cortex_a57_disable_ext_debug
|
||||||
|
@ -132,6 +139,48 @@ func check_errata_813420
|
||||||
b cpu_rev_var_ls
|
b cpu_rev_var_ls
|
||||||
endfunc check_errata_813420
|
endfunc check_errata_813420
|
||||||
|
|
||||||
|
/* ---------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A57 Errata #814670.
|
||||||
|
* This applies only to revision r0p0 of Cortex A57.
|
||||||
|
* Inputs:
|
||||||
|
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||||
|
* Shall clobber: x0-x17
|
||||||
|
* ---------------------------------------------------
|
||||||
|
*/
|
||||||
|
func errata_a57_814670_wa
|
||||||
|
/*
|
||||||
|
* Compare x0 against revision r0p0
|
||||||
|
*/
|
||||||
|
mov x17, x30
|
||||||
|
bl check_errata_814670
|
||||||
|
cbz x0, 1f
|
||||||
|
mrs x1, CORTEX_A57_CPUACTLR_EL1
|
||||||
|
orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
|
||||||
|
msr CORTEX_A57_CPUACTLR_EL1, x1
|
||||||
|
isb
|
||||||
|
1:
|
||||||
|
ret x17
|
||||||
|
endfunc errata_a57_814670_wa
|
||||||
|
|
||||||
|
func check_errata_814670
|
||||||
|
mov x1, #0x00
|
||||||
|
b cpu_rev_var_ls
|
||||||
|
endfunc check_errata_814670
|
||||||
|
|
||||||
|
/* ----------------------------------------------------
|
||||||
|
* Errata Workaround for Cortex A57 Errata #817169.
|
||||||
|
* This applies only to revision <= r0p1 of Cortex A57.
|
||||||
|
* ----------------------------------------------------
|
||||||
|
*/
|
||||||
|
func check_errata_817169
|
||||||
|
/*
|
||||||
|
* Even though this is only needed for revision <= r0p1, it
|
||||||
|
* is always applied because of the low cost of the workaround.
|
||||||
|
*/
|
||||||
|
mov x0, #ERRATA_APPLIES
|
||||||
|
ret
|
||||||
|
endfunc check_errata_817169
|
||||||
|
|
||||||
/* --------------------------------------------------------------------
|
/* --------------------------------------------------------------------
|
||||||
* Disable the over-read from the LDNP instruction.
|
* Disable the over-read from the LDNP instruction.
|
||||||
*
|
*
|
||||||
|
@ -366,6 +415,11 @@ func cortex_a57_reset_func
|
||||||
bl errata_a57_813420_wa
|
bl errata_a57_813420_wa
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ERRATA_A57_814670
|
||||||
|
mov x0, x18
|
||||||
|
bl errata_a57_814670_wa
|
||||||
|
#endif
|
||||||
|
|
||||||
#if A57_DISABLE_NON_TEMPORAL_HINT
|
#if A57_DISABLE_NON_TEMPORAL_HINT
|
||||||
mov x0, x18
|
mov x0, x18
|
||||||
bl a57_disable_ldnp_overread
|
bl a57_disable_ldnp_overread
|
||||||
|
@ -537,6 +591,8 @@ func cortex_a57_errata_report
|
||||||
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
||||||
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
||||||
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
||||||
|
report_errata ERRATA_A57_814670, cortex_a57, 814670
|
||||||
|
report_errata ERRATA_A57_817169, cortex_a57, 817169
|
||||||
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
||||||
disable_ldnp_overread
|
disable_ldnp_overread
|
||||||
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
||||||
|
|
|
@ -53,10 +53,22 @@ endif
|
||||||
# These should be enabled by the platform if the erratum workaround needs to be
|
# These should be enabled by the platform if the erratum workaround needs to be
|
||||||
# applied.
|
# applied.
|
||||||
|
|
||||||
|
# Flag to apply erratum 819472 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r0p1 of the Cortex A53 cpu.
|
||||||
|
ERRATA_A53_819472 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 824069 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r0p2 of the Cortex A53 cpu.
|
||||||
|
ERRATA_A53_824069 ?=0
|
||||||
|
|
||||||
# Flag to apply erratum 826319 workaround during reset. This erratum applies
|
# Flag to apply erratum 826319 workaround during reset. This erratum applies
|
||||||
# only to revision <= r0p2 of the Cortex A53 cpu.
|
# only to revision <= r0p2 of the Cortex A53 cpu.
|
||||||
ERRATA_A53_826319 ?=0
|
ERRATA_A53_826319 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 827319 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r0p2 of the Cortex A53 cpu.
|
||||||
|
ERRATA_A53_827319 ?=0
|
||||||
|
|
||||||
# Flag to apply erratum 835769 workaround at compile and link time. This
|
# Flag to apply erratum 835769 workaround at compile and link time. This
|
||||||
# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
|
# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
|
||||||
# workaround can lead the linker to create "*.stub" sections.
|
# workaround can lead the linker to create "*.stub" sections.
|
||||||
|
@ -79,6 +91,26 @@ ERRATA_A53_843419 ?=0
|
||||||
# of by the rich OS.
|
# of by the rich OS.
|
||||||
ERRATA_A53_855873 ?=0
|
ERRATA_A53_855873 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 768277 workaround during reset. This erratum applies
|
||||||
|
# only to revision r0p0 of the Cortex A55 cpu.
|
||||||
|
ERRATA_A55_768277 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 778703 workaround during reset. This erratum applies
|
||||||
|
# only to revision r0p0 of the Cortex A55 cpu.
|
||||||
|
ERRATA_A55_778703 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 798797 workaround during reset. This erratum applies
|
||||||
|
# only to revision r0p0 of the Cortex A55 cpu.
|
||||||
|
ERRATA_A55_798797 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 846532 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r0p1 of the Cortex A55 cpu.
|
||||||
|
ERRATA_A55_846532 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 903758 workaround during reset. This erratum applies
|
||||||
|
# only to revision <= r0p1 of the Cortex A55 cpu.
|
||||||
|
ERRATA_A55_903758 ?=0
|
||||||
|
|
||||||
# Flag to apply erratum 806969 workaround during reset. This erratum applies
|
# Flag to apply erratum 806969 workaround during reset. This erratum applies
|
||||||
# only to revision r0p0 of the Cortex A57 cpu.
|
# only to revision r0p0 of the Cortex A57 cpu.
|
||||||
ERRATA_A57_806969 ?=0
|
ERRATA_A57_806969 ?=0
|
||||||
|
@ -91,6 +123,14 @@ ERRATA_A57_813419 ?=0
|
||||||
# only to revision r0p0 of the Cortex A57 cpu.
|
# only to revision r0p0 of the Cortex A57 cpu.
|
||||||
ERRATA_A57_813420 ?=0
|
ERRATA_A57_813420 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 814670 workaround during reset. This erratum applies
|
||||||
|
# only to revision r0p0 of the Cortex A57 cpu.
|
||||||
|
ERRATA_A57_814670 ?=0
|
||||||
|
|
||||||
|
# Flag to apply erratum 817169 workaround during power down. This erratum
|
||||||
|
# applies only to revision <= r0p1 of the Cortex A57 cpu.
|
||||||
|
ERRATA_A57_817169 ?=0
|
||||||
|
|
||||||
# Flag to apply erratum 826974 workaround during reset. This erratum applies
|
# Flag to apply erratum 826974 workaround during reset. This erratum applies
|
||||||
# only to revision <= r1p1 of the Cortex A57 cpu.
|
# only to revision <= r1p1 of the Cortex A57 cpu.
|
||||||
ERRATA_A57_826974 ?=0
|
ERRATA_A57_826974 ?=0
|
||||||
|
@ -152,10 +192,22 @@ ERRATA_N1_1043202 ?=1
|
||||||
# higher DSU power consumption on idle.
|
# higher DSU power consumption on idle.
|
||||||
ERRATA_DSU_936184 ?=0
|
ERRATA_DSU_936184 ?=0
|
||||||
|
|
||||||
|
# Process ERRATA_A53_819472 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A53_819472))
|
||||||
|
$(eval $(call add_define,ERRATA_A53_819472))
|
||||||
|
|
||||||
|
# Process ERRATA_A53_824069 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A53_824069))
|
||||||
|
$(eval $(call add_define,ERRATA_A53_824069))
|
||||||
|
|
||||||
# Process ERRATA_A53_826319 flag
|
# Process ERRATA_A53_826319 flag
|
||||||
$(eval $(call assert_boolean,ERRATA_A53_826319))
|
$(eval $(call assert_boolean,ERRATA_A53_826319))
|
||||||
$(eval $(call add_define,ERRATA_A53_826319))
|
$(eval $(call add_define,ERRATA_A53_826319))
|
||||||
|
|
||||||
|
# Process ERRATA_A53_827319 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A53_827319))
|
||||||
|
$(eval $(call add_define,ERRATA_A53_827319))
|
||||||
|
|
||||||
# Process ERRATA_A53_835769 flag
|
# Process ERRATA_A53_835769 flag
|
||||||
$(eval $(call assert_boolean,ERRATA_A53_835769))
|
$(eval $(call assert_boolean,ERRATA_A53_835769))
|
||||||
$(eval $(call add_define,ERRATA_A53_835769))
|
$(eval $(call add_define,ERRATA_A53_835769))
|
||||||
|
@ -172,6 +224,26 @@ $(eval $(call add_define,ERRATA_A53_843419))
|
||||||
$(eval $(call assert_boolean,ERRATA_A53_855873))
|
$(eval $(call assert_boolean,ERRATA_A53_855873))
|
||||||
$(eval $(call add_define,ERRATA_A53_855873))
|
$(eval $(call add_define,ERRATA_A53_855873))
|
||||||
|
|
||||||
|
# Process ERRATA_A55_768277 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A55_768277))
|
||||||
|
$(eval $(call add_define,ERRATA_A55_768277))
|
||||||
|
|
||||||
|
# Process ERRATA_A55_778703 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A55_778703))
|
||||||
|
$(eval $(call add_define,ERRATA_A55_778703))
|
||||||
|
|
||||||
|
# Process ERRATA_A55_798797 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A55_798797))
|
||||||
|
$(eval $(call add_define,ERRATA_A55_798797))
|
||||||
|
|
||||||
|
# Process ERRATA_A55_846532 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A55_846532))
|
||||||
|
$(eval $(call add_define,ERRATA_A55_846532))
|
||||||
|
|
||||||
|
# Process ERRATA_A55_903758 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A55_903758))
|
||||||
|
$(eval $(call add_define,ERRATA_A55_903758))
|
||||||
|
|
||||||
# Process ERRATA_A57_806969 flag
|
# Process ERRATA_A57_806969 flag
|
||||||
$(eval $(call assert_boolean,ERRATA_A57_806969))
|
$(eval $(call assert_boolean,ERRATA_A57_806969))
|
||||||
$(eval $(call add_define,ERRATA_A57_806969))
|
$(eval $(call add_define,ERRATA_A57_806969))
|
||||||
|
@ -184,6 +256,14 @@ $(eval $(call add_define,ERRATA_A57_813419))
|
||||||
$(eval $(call assert_boolean,ERRATA_A57_813420))
|
$(eval $(call assert_boolean,ERRATA_A57_813420))
|
||||||
$(eval $(call add_define,ERRATA_A57_813420))
|
$(eval $(call add_define,ERRATA_A57_813420))
|
||||||
|
|
||||||
|
# Process ERRATA_A57_814670 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A57_814670))
|
||||||
|
$(eval $(call add_define,ERRATA_A57_814670))
|
||||||
|
|
||||||
|
# Process ERRATA_A57_817169 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_A57_817169))
|
||||||
|
$(eval $(call add_define,ERRATA_A57_817169))
|
||||||
|
|
||||||
# Process ERRATA_A57_826974 flag
|
# Process ERRATA_A57_826974 flag
|
||||||
$(eval $(call assert_boolean,ERRATA_A57_826974))
|
$(eval $(call assert_boolean,ERRATA_A57_826974))
|
||||||
$(eval $(call add_define,ERRATA_A57_826974))
|
$(eval $(call add_define,ERRATA_A57_826974))
|
||||||
|
|
|
@ -105,7 +105,10 @@ bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin
|
||||||
./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT)
|
./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT)
|
||||||
|
|
||||||
# Errata workarounds for Cortex-A53:
|
# Errata workarounds for Cortex-A53:
|
||||||
|
ERRATA_A53_819472 := 1
|
||||||
|
ERRATA_A53_824069 := 1
|
||||||
ERRATA_A53_826319 := 1
|
ERRATA_A53_826319 := 1
|
||||||
|
ERRATA_A53_827319 := 1
|
||||||
ERRATA_A53_835769 := 1
|
ERRATA_A53_835769 := 1
|
||||||
ERRATA_A53_836870 := 1
|
ERRATA_A53_836870 := 1
|
||||||
ERRATA_A53_843419 := 1
|
ERRATA_A53_843419 := 1
|
||||||
|
@ -115,6 +118,8 @@ ERRATA_A53_855873 := 1
|
||||||
ERRATA_A57_806969 := 0
|
ERRATA_A57_806969 := 0
|
||||||
ERRATA_A57_813419 := 1
|
ERRATA_A57_813419 := 1
|
||||||
ERRATA_A57_813420 := 1
|
ERRATA_A57_813420 := 1
|
||||||
|
ERRATA_A57_814670 := 1
|
||||||
|
ERRATA_A57_817169 := 1
|
||||||
ERRATA_A57_826974 := 1
|
ERRATA_A57_826974 := 1
|
||||||
ERRATA_A57_826977 := 1
|
ERRATA_A57_826977 := 1
|
||||||
ERRATA_A57_828024 := 1
|
ERRATA_A57_828024 := 1
|
||||||
|
|
Loading…
Reference in New Issue