plat/fvp: Support for extracting UART serial node info from DT
This patch introduces the populate function which leverages a new driver to extract base address and clk frequency properties of the uart serial node from HW_CONFIG device tree. This patch also introduces fdt helper API fdtw_translate_address() which helps in performing address translation. Change-Id: I053628065ebddbde0c9cb3aa93d838619f502ee3 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This commit is contained in:
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f1a1653ce1
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@ -341,3 +341,199 @@ int fdt_get_stdout_node_offset(const void *dtb)
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return fdt_path_offset(dtb, path);
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return fdt_path_offset(dtb, path);
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}
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}
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/*******************************************************************************
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* Only devices which are direct children of root node use CPU address domain.
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* All other devices use addresses that are local to the device node and cannot
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* directly used by CPU. Device tree provides an address translation mechanism
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* through "ranges" property which provides mappings from local address space to
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* parent address space. Since a device could be a child of a child node to the
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* root node, there can be more than one level of address translation needed to
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* map the device local address space to CPU address space.
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* fdtw_translate_address() API performs address translation of a local address
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* to a global address with help of various helper functions.
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******************************************************************************/
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static bool fdtw_xlat_hit(const uint32_t *value, int child_addr_size,
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int parent_addr_size, int range_size, uint64_t base_address,
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uint64_t *translated_addr)
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{
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uint64_t local_address, parent_address, addr_range;
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local_address = fdt_read_prop_cells(value, child_addr_size);
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parent_address = fdt_read_prop_cells(value + child_addr_size,
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parent_addr_size);
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addr_range = fdt_read_prop_cells(value + child_addr_size +
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parent_addr_size,
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range_size);
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VERBOSE("DT: Address %llx mapped to %llx with range %llx\n",
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local_address, parent_address, addr_range);
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/* Perform range check */
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if ((base_address < local_address) ||
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(base_address >= local_address + addr_range)) {
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return false;
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}
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/* Found hit for the addr range that needs to be translated */
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*translated_addr = parent_address + (base_address - local_address);
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VERBOSE("DT: child address %llx mapped to %llx in parent bus\n",
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local_address, parent_address);
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return true;
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}
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#define ILLEGAL_ADDR ULL(~0)
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static uint64_t fdtw_search_all_xlat_entries(const void *dtb,
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const struct fdt_property *ranges_prop,
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int local_bus, uint64_t base_address)
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{
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uint64_t translated_addr;
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const uint32_t *next_entry;
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int parent_bus_node, nxlat_entries, length;
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int self_addr_cells, parent_addr_cells, self_size_cells, ncells_xlat;
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/*
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* The number of cells in one translation entry in ranges is the sum of
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* the following values:
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* self#address-cells + parent#address-cells + self#size-cells
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* Ex: the iofpga ranges property has one translation entry with 4 cells
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* They represent iofpga#addr-cells + motherboard#addr-cells + iofpga#size-cells
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* = 1 + 2 + 1
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*/
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parent_bus_node = fdt_parent_offset(dtb, local_bus);
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self_addr_cells = fdt_address_cells(dtb, local_bus);
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self_size_cells = fdt_size_cells(dtb, local_bus);
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parent_addr_cells = fdt_address_cells(dtb, parent_bus_node);
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/* Number of cells per translation entry i.e., mapping */
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ncells_xlat = self_addr_cells + parent_addr_cells + self_size_cells;
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assert(ncells_xlat > 0);
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/*
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* Find the number of translations(mappings) specified in the current
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* `ranges` property. Note that length represents number of bytes and
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* is stored in big endian mode.
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*/
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length = fdt32_to_cpu(ranges_prop->len);
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nxlat_entries = (length/sizeof(uint32_t))/ncells_xlat;
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assert(nxlat_entries > 0);
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next_entry = (const uint32_t *)ranges_prop->data;
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/* Iterate over the entries in the "ranges" */
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for (int i = 0; i < nxlat_entries; i++) {
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if (fdtw_xlat_hit(next_entry, self_addr_cells,
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parent_addr_cells, self_size_cells, base_address,
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&translated_addr)){
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return translated_addr;
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}
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next_entry = next_entry + ncells_xlat;
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}
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INFO("DT: No translation found for address %llx in node %s\n",
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base_address, fdt_get_name(dtb, local_bus, NULL));
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return ILLEGAL_ADDR;
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}
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/*******************************************************************************
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* address mapping needs to be done recursively starting from current node to
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* root node through all intermediate parent nodes.
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* Sample device tree is shown here:
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smb@0,0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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motherboard {
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arm,v2m-memory-map = "rs1";
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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iofpga@3,00000000 {
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compatible = "arm,amba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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v2m_serial1: uart@a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <0 6 4>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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};
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};
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* As seen above, there are 3 levels of address translations needed. An empty
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* `ranges` property denotes identity mapping (as seen in `motherboard` node).
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* Each ranges property can map a set of child addresses to parent bus. Hence
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* there can be more than 1 (translation) entry in the ranges property as seen
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* in the `smb` node which has 6 translation entries.
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******************************************************************************/
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/* Recursive implementation */
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uint64_t fdtw_translate_address(const void *dtb, int node,
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uint64_t base_address)
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{
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int length, local_bus_node;
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const char *node_name;
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uint64_t global_address;
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local_bus_node = fdt_parent_offset(dtb, node);
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node_name = fdt_get_name(dtb, local_bus_node, NULL);
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/*
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* In the example given above, starting from the leaf node:
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* uart@a000 represents the current node
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* iofpga@3,00000000 represents the local bus
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* motherboard represents the parent bus
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*/
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/* Read the ranges property */
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const struct fdt_property *property = fdt_get_property(dtb,
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local_bus_node, "ranges", &length);
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if (property == NULL) {
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if (local_bus_node == 0) {
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/*
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* root node doesn't have range property as addresses
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* are in CPU address space.
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*/
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return base_address;
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}
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INFO("DT: Couldn't find ranges property in node %s\n",
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node_name);
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return ILLEGAL_ADDR;
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} else if (length == 0) {
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/* empty ranges indicates identity map to parent bus */
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return fdtw_translate_address(dtb, local_bus_node, base_address);
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}
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VERBOSE("DT: Translation lookup in node %s at offset %d\n", node_name,
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local_bus_node);
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global_address = fdtw_search_all_xlat_entries(dtb, property,
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local_bus_node, base_address);
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if (global_address == ILLEGAL_ADDR) {
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return ILLEGAL_ADDR;
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}
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/* Translate the local device address recursively */
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return fdtw_translate_address(dtb, local_bus_node, global_address);
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}
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@ -34,4 +34,7 @@ int fdt_get_reg_props_by_name(const void *dtb, int node, const char *name,
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uintptr_t *base, size_t *size);
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uintptr_t *base, size_t *size);
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int fdt_get_stdout_node_offset(const void *dtb);
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int fdt_get_stdout_node_offset(const void *dtb);
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uint64_t fdtw_translate_address(const void *dtb, int bus_node,
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uint64_t base_address);
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#endif /* FDT_WRAPPERS_H */
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#endif /* FDT_WRAPPERS_H */
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@ -13,6 +13,9 @@
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struct gicv3_config_t gicv3_config;
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struct gicv3_config_t gicv3_config;
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struct hw_topology_t soc_topology;
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struct hw_topology_t soc_topology;
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struct uart_serial_config_t uart_serial_config;
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#define ILLEGAL_ADDR ULL(~0)
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int fconf_populate_gicv3_config(uintptr_t config)
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int fconf_populate_gicv3_config(uintptr_t config)
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{
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{
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@ -147,7 +150,8 @@ int fconf_populate_topology(uintptr_t config)
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return -1;
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return -1;
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}
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}
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INFO("CLUSTER ID: %d cpu-count: %d\n", cluster_count, cpus_per_cluster[cluster_count]);
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VERBOSE("CLUSTER ID: %d cpu-count: %d\n", cluster_count,
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cpus_per_cluster[cluster_count]);
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/* Find the maximum number of cpus in any cluster */
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/* Find the maximum number of cpus in any cluster */
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max_cpu_per_cluster = MAX(max_cpu_per_cluster, cpus_per_cluster[cluster_count]);
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max_cpu_per_cluster = MAX(max_cpu_per_cluster, cpus_per_cluster[cluster_count]);
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@ -170,5 +174,95 @@ int fconf_populate_topology(uintptr_t config)
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return 0;
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return 0;
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}
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}
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int fconf_populate_uart_config(uintptr_t config)
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{
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int uart_node, node, err;
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uintptr_t addr;
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const char *path;
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uint32_t phandle;
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uint64_t translated_addr;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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/*
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* uart child node is indirectly referenced through its path which is
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* specified in the `serial1` property of the "aliases" node.
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* Note that TF-A boot console is mapped to serial0 while runtime
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* console is mapped to serial1.
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*/
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path = fdt_get_alias(hw_config_dtb, "serial1");
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if (path == NULL) {
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ERROR("FCONF: Could not read serial1 property in aliases node\n");
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return -1;
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}
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/* Find the offset of the uart serial node */
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uart_node = fdt_path_offset(hw_config_dtb, path);
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if (uart_node < 0) {
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ERROR("FCONF: Failed to locate uart serial node using its path\n");
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return -1;
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}
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/* uart serial node has its offset and size of address in reg property */
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err = fdt_get_reg_props_by_index(hw_config_dtb, uart_node, 0, &addr,
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NULL);
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if (err < 0) {
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ERROR("FCONF: Failed to read reg property of '%s' node\n",
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"uart serial");
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return err;
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}
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VERBOSE("FCONF: UART node address: %lx\n", addr);
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/*
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* Perform address translation of local device address to CPU address
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* domain.
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*/
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translated_addr = fdtw_translate_address(hw_config_dtb,
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uart_node, (uint64_t)addr);
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if (translated_addr == ILLEGAL_ADDR) {
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ERROR("FCONF: failed to translate UART node base address");
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return -1;
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}
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uart_serial_config.uart_base = translated_addr;
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VERBOSE("FCONF: UART serial device base address: %llx\n",
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uart_serial_config.uart_base);
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/*
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* The phandle of the DT node which captures the clock info of uart
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* serial node is specified in the "clocks" property.
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*/
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err = fdt_read_uint32(hw_config_dtb, uart_node, "clocks", &phandle);
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if (err < 0) {
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ERROR("FCONF: Could not read clocks property in uart serial node\n");
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return err;
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}
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node = fdt_node_offset_by_phandle(hw_config_dtb, phandle);
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if (node < 0) {
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ERROR("FCONF: Failed to locate clk node using its path\n");
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return node;
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}
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/*
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* Retrieve clock frequency. We assume clock provider generates a fixed
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* clock.
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*/
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err = fdt_read_uint32(hw_config_dtb, node, "clock-frequency",
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&uart_serial_config.uart_clk);
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if (err < 0) {
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ERROR("FCONF: Could not read clock-frequency property in clk node\n");
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return err;
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}
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VERBOSE("FCONF: UART serial device clk frequency: %x\n",
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uart_serial_config.uart_clk);
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return 0;
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}
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FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
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@ -14,6 +14,8 @@
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#define hw_config__topology_getter(prop) soc_topology.prop
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#define hw_config__topology_getter(prop) soc_topology.prop
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#define hw_config__uart_serial_config_getter(prop) uart_serial_config.prop
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struct gicv3_config_t {
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struct gicv3_config_t {
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uintptr_t gicd_base;
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uintptr_t gicd_base;
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uintptr_t gicr_base;
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uintptr_t gicr_base;
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@ -26,10 +28,17 @@ struct hw_topology_t {
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uint32_t plat_max_pwr_level;
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uint32_t plat_max_pwr_level;
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};
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};
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struct uart_serial_config_t {
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uint64_t uart_base;
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uint32_t uart_clk;
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};
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int fconf_populate_gicv3_config(uintptr_t config);
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int fconf_populate_gicv3_config(uintptr_t config);
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int fconf_populate_topology(uintptr_t config);
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int fconf_populate_topology(uintptr_t config);
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int fconf_populate_uart_config(uintptr_t config);
|
||||||
|
|
||||||
extern struct gicv3_config_t gicv3_config;
|
extern struct gicv3_config_t gicv3_config;
|
||||||
extern struct hw_topology_t soc_topology;
|
extern struct hw_topology_t soc_topology;
|
||||||
|
extern struct uart_serial_config_t uart_serial_config;
|
||||||
|
|
||||||
#endif /* FCONF_HW_CONFIG_GETTER_H */
|
#endif /* FCONF_HW_CONFIG_GETTER_H */
|
||||||
|
|
|
@ -16,6 +16,7 @@
|
||||||
|
|
||||||
rom rom_lib_init
|
rom rom_lib_init
|
||||||
fdt fdt_getprop
|
fdt fdt_getprop
|
||||||
|
fdt fdt_get_property
|
||||||
fdt fdt_getprop_namelen
|
fdt fdt_getprop_namelen
|
||||||
fdt fdt_setprop_inplace
|
fdt fdt_setprop_inplace
|
||||||
fdt fdt_check_header
|
fdt fdt_check_header
|
||||||
|
@ -31,6 +32,9 @@ fdt fdt_size_cells
|
||||||
fdt fdt_parent_offset
|
fdt fdt_parent_offset
|
||||||
fdt fdt_stringlist_search
|
fdt fdt_stringlist_search
|
||||||
fdt fdt_get_alias_namelen
|
fdt fdt_get_alias_namelen
|
||||||
|
fdt fdt_get_name
|
||||||
|
fdt fdt_get_alias
|
||||||
|
fdt fdt_node_offset_by_phandle
|
||||||
mbedtls mbedtls_asn1_get_alg
|
mbedtls mbedtls_asn1_get_alg
|
||||||
mbedtls mbedtls_asn1_get_alg_null
|
mbedtls mbedtls_asn1_get_alg_null
|
||||||
mbedtls mbedtls_asn1_get_bitstring_null
|
mbedtls mbedtls_asn1_get_bitstring_null
|
||||||
|
|
|
@ -16,6 +16,7 @@
|
||||||
|
|
||||||
rom rom_lib_init
|
rom rom_lib_init
|
||||||
fdt fdt_getprop
|
fdt fdt_getprop
|
||||||
|
fdt fdt_get_property
|
||||||
fdt fdt_getprop_namelen
|
fdt fdt_getprop_namelen
|
||||||
fdt fdt_setprop_inplace
|
fdt fdt_setprop_inplace
|
||||||
fdt fdt_check_header
|
fdt fdt_check_header
|
||||||
|
@ -28,6 +29,9 @@ fdt fdt_stringlist_search
|
||||||
fdt fdt_get_alias_namelen
|
fdt fdt_get_alias_namelen
|
||||||
fdt fdt_path_offset
|
fdt fdt_path_offset
|
||||||
fdt fdt_path_offset_namelen
|
fdt fdt_path_offset_namelen
|
||||||
|
fdt fdt_get_name
|
||||||
|
fdt fdt_get_alias
|
||||||
|
fdt fdt_node_offset_by_phandle
|
||||||
mbedtls mbedtls_asn1_get_alg
|
mbedtls mbedtls_asn1_get_alg
|
||||||
mbedtls mbedtls_asn1_get_alg_null
|
mbedtls mbedtls_asn1_get_alg_null
|
||||||
mbedtls mbedtls_asn1_get_bitstring_null
|
mbedtls mbedtls_asn1_get_bitstring_null
|
||||||
|
|
Loading…
Reference in New Issue