feat(plat/qti/sc7280): support for qti sc7280 plat
new qti platform sc7280 support addition Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Change-Id: I3dd99d8744a6c313f7dfbbee7ae2cbd6f21656c1
This commit is contained in:
Saurabh Gorecha
Joanna Farley
parent
95ef4a0f6b
commit
46ee50e0b3
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@ -1,8 +1,8 @@
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Qualcomm Technologies, Inc.
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===========================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QTI SC7180.
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QTI SC7180,
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SC7280.
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Boot Trace
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-------------
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@ -38,4 +38,6 @@ is picked. qtiseclib with stub implementation doesn't boot device. This was
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added to satisfy compilation.
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QTISELIB for SC7180 is available at
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`link <https://review.coreboot.org/cgit/qc_blobs.git/plain/sc7180/qtiseclib/libqtisec.a>`__
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`link <https://github.com/coreboot/qc_blobs/blob/master/sc7180/qtiseclib/libqtisec.a?raw=true>`__
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QTISELIB for SC7280 is available at
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`link <https://github.com/coreboot/qc_blobs/blob/master/sc7280/qtiseclib/libqtisec.a?raw=true>`__
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -13,4 +13,10 @@
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/* KRYO-4xx Silver MIDR */
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#define QTI_KRYO4_SILVER_MIDR 0x517F805D
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/* KRYO-6xx Gold MIDR */
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#define QTI_KRYO6_GOLD_MIDR 0x412FD410
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/* KRYO-6xx Silver MIDR */
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#define QTI_KRYO6_SILVER_MIDR 0x412FD050
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#endif /* QTI_CPU_H */
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@ -0,0 +1,83 @@
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/*
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* Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <qti_cpu.h>
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.p2align 3
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/* -------------------------------------------------
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* The CPU Ops reset function for Kryo-3 Gold
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* -------------------------------------------------
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*/
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func qti_kryo6_gold_reset_func
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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adr x0, wa_cve_2017_5715_bpiall_vbar
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msr vbar_el3, x0
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isb
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#endif
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mov x19, x30
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bl qtiseclib_kryo6_gold_reset_asm
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ret x19
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endfunc qti_kryo6_gold_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Kryo-3 Gold
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* ----------------------------------------------------
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*/
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func qti_kryo6_gold_core_pwr_dwn
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ret
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endfunc qti_kryo6_gold_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Kryo-3 Gold
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* -------------------------------------------------------
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*/
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func qti_kryo6_gold_cluster_pwr_dwn
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ret
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endfunc qti_kryo6_gold_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Kryo4 Gold. Must follow AAPCS.
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*/
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func qti_kryo6_gold_errata_report
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/* TODO : Need to add support. Required only for debug bl31 image.*/
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ret
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endfunc qti_kryo6_gold_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides kryo4_gold specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ASCII and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.qti_kryo4_gold_regs, "aS"
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qti_kryo6_gold_regs: /* The ASCII list of register names to be reported */
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.asciz ""
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func qti_kryo6_gold_cpu_reg_dump
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adr x6, qti_kryo6_gold_regs
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ret
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endfunc qti_kryo6_gold_cpu_reg_dump
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declare_cpu_ops qti_kryo6_gold, QTI_KRYO6_GOLD_MIDR, \
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qti_kryo6_gold_reset_func, \
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qti_kryo6_gold_core_pwr_dwn, \
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qti_kryo6_gold_cluster_pwr_dwn
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@ -0,0 +1,79 @@
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/*
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* Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <qti_cpu.h>
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.p2align 3
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/* -------------------------------------------------
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* The CPU Ops reset function for Kryo-3 Silver
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* -------------------------------------------------
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*/
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func qti_kryo6_silver_reset_func
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mov x19, x30
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bl qtiseclib_kryo6_silver_reset_asm
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ret x19
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endfunc qti_kryo6_silver_reset_func
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/* ------------------------------------------------------
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* The CPU Ops core power down function for Kryo-3 Silver
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* ------------------------------------------------------
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*/
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func qti_kryo6_silver_core_pwr_dwn
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ret
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endfunc qti_kryo6_silver_core_pwr_dwn
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/* ---------------------------------------------------------
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* The CPU Ops cluster power down function for Kryo-3 Silver
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* ---------------------------------------------------------
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*/
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func qti_kryo6_silver_cluster_pwr_dwn
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ret
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endfunc qti_kryo6_silver_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Kryo4 Silver. Must follow AAPCS.
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*/
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func qti_kryo6_silver_errata_report
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/* TODO : Need to add support. Required only for debug bl31 image.*/
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ret
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endfunc qti_kryo6_silver_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides kryo4_silver specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ASCII and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.qti_kryo4_silver_regs, "aS"
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qti_kryo6_silver_regs: /* The ASCII list of register names to be reported */
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.asciz ""
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func qti_kryo6_silver_cpu_reg_dump
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adr x6, qti_kryo6_silver_regs
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ret
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endfunc qti_kryo6_silver_cpu_reg_dump
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declare_cpu_ops qti_kryo6_silver, QTI_KRYO6_SILVER_MIDR, \
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qti_kryo6_silver_reset_func, \
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qti_kryo6_silver_core_pwr_dwn, \
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qti_kryo6_silver_cluster_pwr_dwn
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -72,6 +72,16 @@ static const interrupt_prop_t qti_interrupt_props[] = {
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INTR_PROP_DESC(QTISECLIB_INT_ID_MMSS_NOC_ERROR,
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GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#ifdef QTISECLIB_INT_ID_LPASS_AGNOC_ERROR
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INTR_PROP_DESC(QTISECLIB_INT_ID_LPASS_AGNOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#endif
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#ifdef QTISECLIB_INT_ID_NSP_NOC_ERROR
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INTR_PROP_DESC(QTISECLIB_INT_ID_NSP_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
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INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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#endif
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};
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const gicv3_driver_data_t qti_gic_data = {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -49,6 +49,14 @@ void qtiseclib_cpuss_reset_asm(uint32_t bl31_cold_boot_state);
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*/
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void qtiseclib_kryo4_gold_reset_asm(void);
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/*
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* Execute CPU (Kryo46 gold) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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*
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* Clobbers: x0 - x16
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*/
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void qtiseclib_kryo6_gold_reset_asm(void);
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/*
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* Execute CPU (Kryo4 silver) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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@ -57,6 +65,14 @@ void qtiseclib_kryo4_gold_reset_asm(void);
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*/
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void qtiseclib_kryo4_silver_reset_asm(void);
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/*
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* Execute CPU (Kryo6 silver) specific reset handler / system initialization.
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* This takes care of executing required CPU errata's.
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*
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* Clobbers: x0 - x16
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*/
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void qtiseclib_kryo6_silver_reset_asm(void);
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/*
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* C Api's
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*/
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/*
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __QTISECLIB_DEFS_PLAT_H__
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#define __QTISECLIB_DEFS_PLAT_H__
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#define QTISECLIB_PLAT_CLUSTER_COUNT 1
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#define QTISECLIB_PLAT_CORE_COUNT 8
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#define BL31_BASE 0xC0000000
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#define BL31_SIZE 0x00100000
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/*----------------------------------------------------------------------------*/
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/* AOP CMD DB address space for mapping */
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/*----------------------------------------------------------------------------*/
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#define QTI_AOP_CMD_DB_BASE 0x80860000
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#define QTI_AOP_CMD_DB_SIZE 0x00020000
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/* Chipset specific secure interrupt number/ID defs. */
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#define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204)
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#define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC (0xE6)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC (0xE7)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC (0xE8)
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#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC (0xE9)
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#define QTISECLIB_INT_ID_XPU_SEC (0xE3)
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#define QTISECLIB_INT_ID_XPU_NON_SEC (0xE4)
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//NOC INterrupt
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#define QTISECLIB_INT_ID_A1_NOC_ERROR (0xC9)
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#define QTISECLIB_INT_ID_A2_NOC_ERROR (0xEA)
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#define QTISECLIB_INT_ID_CONFIG_NOC_ERROR (0xE2)
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#define QTISECLIB_INT_ID_DC_NOC_ERROR (0x122)
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#define QTISECLIB_INT_ID_MEM_NOC_ERROR (0x6C)
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#define QTISECLIB_INT_ID_SYSTEM_NOC_ERROR (0xC8)
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#define QTISECLIB_INT_ID_MMSS_NOC_ERROR (0xBA)
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#define QTISECLIB_INT_ID_LPASS_AGNOC_ERROR (0x143)
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#define QTISECLIB_INT_ID_NSP_NOC_ERROR (0x1CE)
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#endif /* __QTISECLIB_DEFS_PLAT_H__ */
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@ -132,6 +132,10 @@ void qtiseclib_cb_get_ns_ctx(qtiseclib_dbg_a64_ctxt_regs_type *qti_ns_ctx)
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void *ctx;
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ctx = cm_get_context(NON_SECURE);
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if (ctx) {
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/* nothing to be done w/o ns context */
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return;
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}
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qti_ns_ctx->spsr_el3 =
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read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3);
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@ -0,0 +1,194 @@
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/*
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* Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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/* Enable the dynamic translation tables library. */
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#define PLAT_XLAT_TABLES_DYNAMIC 1
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#include <common_def.h>
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#include <qti_board_def.h>
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#include <qtiseclib_defs_plat.h>
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/*
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* MPIDR_PRIMARY_CPU
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* You just need to have the correct core_affinity_val i.e. [7:0]
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* and cluster_affinity_val i.e. [15:8]
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* the other bits will be ignored
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*/
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/*----------------------------------------------------------------------------*/
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#define MPIDR_PRIMARY_CPU 0x0000
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/*----------------------------------------------------------------------------*/
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#define QTI_PWR_LVL0 MPIDR_AFFLVL0
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#define QTI_PWR_LVL1 MPIDR_AFFLVL1
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#define QTI_PWR_LVL2 MPIDR_AFFLVL2
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#define QTI_PWR_LVL3 MPIDR_AFFLVL3
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/*
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* Macros for local power states encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define QTI_LOCAL_STATE_RUN 0
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/*
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* Local power state for clock-gating. Valid only for CPU and not cluster power
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* domains
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*/
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#define QTI_LOCAL_STATE_STB 1
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/*
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* Local power state for retention. Valid for CPU and cluster power
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* domains
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*/
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#define QTI_LOCAL_STATE_RET 2
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/*
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* Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC
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* power domains
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*/
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#define QTI_LOCAL_STATE_OFF 3
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/*
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* Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC
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* power domains
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*/
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#define QTI_LOCAL_STATE_DEEPOFF 4
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF
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/******************************************************************************
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* Required platform porting definitions common to all ARM standard platforms
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*****************************************************************************/
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/*
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* Platform specific page table and MMU setup constants.
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*/
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#define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36)
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
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/*
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* One cache line needed for bakery locks on ARM platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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/*----------------------------------------------------------------------------*/
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/* PSCI power domain topology definitions */
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/*----------------------------------------------------------------------------*/
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/* One domain each to represent RSC and PDC level */
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#define PLAT_PDC_COUNT 1
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#define PLAT_RSC_COUNT 1
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/* There is one top-level FCM cluster */
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#define PLAT_CLUSTER_COUNT 1
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/* No. of cores in the FCM cluster */
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#define PLAT_CLUSTER0_CORE_COUNT 8
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#define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT)
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#define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\
|
||||
PLAT_RSC_COUNT +\
|
||||
PLAT_CLUSTER_COUNT +\
|
||||
PLATFORM_CORE_COUNT)
|
||||
|
||||
#define PLAT_MAX_PWR_LVL 3
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Memory mapped Generic timer interfaces */
|
||||
/*****************************************************************************/
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* GIC-600 constants */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#define BASE_GICD_BASE 0x17A00000
|
||||
#define BASE_GICR_BASE 0x17A60000
|
||||
#define BASE_GICC_BASE 0x0
|
||||
#define BASE_GICH_BASE 0x0
|
||||
#define BASE_GICV_BASE 0x0
|
||||
|
||||
#define QTI_GICD_BASE BASE_GICD_BASE
|
||||
#define QTI_GICR_BASE BASE_GICR_BASE
|
||||
#define QTI_GICC_BASE BASE_GICC_BASE
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* UART related constants. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */
|
||||
#define GENI4_CFG 0x0
|
||||
#define GENI4_IMAGE_REGS 0x100
|
||||
#define GENI4_DATA 0x600
|
||||
|
||||
/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */
|
||||
#define GENI_STATUS_REG (GENI4_CFG + 0x00000040)
|
||||
#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1)
|
||||
#define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170)
|
||||
/* MASTER/TX ENGINE REGISTERS */
|
||||
#define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000)
|
||||
/* FIFO, STATUS REGISTERS AND MASKS */
|
||||
#define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100)
|
||||
|
||||
#define GENI_M_CMD_TX (0x08000000)
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* Device address space for mapping. Excluding starting 4K */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#define QTI_DEVICE_BASE 0x1000
|
||||
#define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL31 at DDR as per memory map. BL31_BASE is calculated using the
|
||||
* current BL31 debug size plus a little space for growth.
|
||||
*/
|
||||
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* AOSS registers */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#define QTI_PS_HOLD_REG 0x0C264000
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* AOP CMD DB address space for mapping */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#define QTI_AOP_CMD_DB_BASE 0x80860000
|
||||
#define QTI_AOP_CMD_DB_SIZE 0x00020000
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* SOC hw version register */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#define QTI_SOC_VERSION U(0x7280)
|
||||
#define QTI_SOC_VERSION_MASK U(0xFFFF)
|
||||
#define QTI_SOC_REVISION_REG 0x1FC8000
|
||||
#define QTI_SOC_REVISION_MASK U(0xFFFF)
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef QTI_RNG_IO_H
|
||||
#define QTI_RNG_IO_H
|
||||
|
||||
#define SEC_PRNG_STATUS 0x10D1004
|
||||
#define SEC_PRNG_STATUS_DATA_AVAIL_BMSK 0x1
|
||||
#define SEC_PRNG_DATA_OUT 0x10D1000
|
||||
|
||||
|
||||
#endif /* QTI_RNG_IO_H */
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef QTI_SECURE_IO_CFG_H
|
||||
#define QTI_SECURE_IO_CFG_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* List of peripheral/IO memory areas that are protected from
|
||||
* non-secure world but not required to be secure.
|
||||
*/
|
||||
|
||||
#define APPS_SMMU_TBU_PWR_STATUS 0x15002204
|
||||
#define APPS_SMMU_CUSTOM_CFG 0x15002300
|
||||
#define APPS_SMMU_STATS_SYNC_INV_TBU_ACK 0x150025DC
|
||||
#define APPS_SMMU_SAFE_SEC_CFG 0x15002648
|
||||
#define APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x15002670
|
||||
|
||||
static const uintptr_t qti_secure_io_allowed_regs[] = {
|
||||
APPS_SMMU_TBU_PWR_STATUS,
|
||||
APPS_SMMU_CUSTOM_CFG,
|
||||
APPS_SMMU_STATS_SYNC_INV_TBU_ACK,
|
||||
APPS_SMMU_SAFE_SEC_CFG,
|
||||
APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
|
||||
};
|
||||
|
||||
#endif /* QTI_SECURE_IO_CFG_H */
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
#
|
||||
# Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Make for SC7280 QTI platform.
|
||||
|
||||
QTI_PLAT_PATH := plat/qti
|
||||
CHIPSET := ${PLAT}
|
||||
|
||||
# Turn On Separate code & data.
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
USE_COHERENT_MEM := 1
|
||||
WARMBOOT_ENABLE_DCACHE_EARLY := 1
|
||||
|
||||
# Disable the PSCI platform compatibility layer
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
|
||||
# Enable PSCI v1.0 extended state ID format
|
||||
PSCI_EXTENDED_STATE_ID := 1
|
||||
ARM_RECOM_STATE_ID_ENC := 1
|
||||
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
PROGRAMMABLE_RESET_ADDRESS := 1
|
||||
|
||||
RESET_TO_BL31 := 0
|
||||
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
QTI_SDI_BUILD := 0
|
||||
$(eval $(call assert_boolean,QTI_SDI_BUILD))
|
||||
$(eval $(call add_define,QTI_SDI_BUILD))
|
||||
|
||||
#disable CTX_INCLUDE_AARCH32_REGS to support sc7280 gold cores
|
||||
override CTX_INCLUDE_AARCH32_REGS := 0
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
|
||||
# Enable stack protector.
|
||||
ENABLE_STACK_PROTECTOR := strong
|
||||
|
||||
|
||||
QTI_EXTERNAL_INCLUDES := -I${QTI_PLAT_PATH}/${CHIPSET}/inc \
|
||||
-I${QTI_PLAT_PATH}/common/inc \
|
||||
-I${QTI_PLAT_PATH}/common/inc/$(ARCH) \
|
||||
-I${QTI_PLAT_PATH}/qtiseclib/inc \
|
||||
-I${QTI_PLAT_PATH}/qtiseclib/inc/${CHIPSET} \
|
||||
|
||||
QTI_BL31_SOURCES := $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_helpers.S \
|
||||
$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo6_silver.S \
|
||||
$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo6_gold.S \
|
||||
$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_uart_console.S \
|
||||
$(QTI_PLAT_PATH)/common/src/pm8998.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_stack_protector.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_common.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_bl31_setup.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_gic_v3.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_interrupt_svc.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_syscall.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_topology.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_pm.c \
|
||||
$(QTI_PLAT_PATH)/common/src/qti_rng.c \
|
||||
$(QTI_PLAT_PATH)/common/src/spmi_arb.c \
|
||||
$(QTI_PLAT_PATH)/qtiseclib/src/qtiseclib_cb_interface.c \
|
||||
|
||||
|
||||
PLAT_INCLUDES := -Iinclude/plat/common/ \
|
||||
|
||||
PLAT_INCLUDES += ${QTI_EXTERNAL_INCLUDES}
|
||||
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
|
||||
plat/common/aarch64/crash_console_helpers.S \
|
||||
common/desc_image_load.c \
|
||||
lib/bl_aux_params/bl_aux_params.c \
|
||||
|
||||
include lib/coreboot/coreboot.mk
|
||||
|
||||
#PSCI Sources.
|
||||
PSCI_SOURCES := plat/common/plat_psci_common.c \
|
||||
|
||||
# GIC-600 configuration
|
||||
GICV3_SUPPORT_GIC600 := 1
|
||||
# Include GICv3 driver files
|
||||
include drivers/arm/gic/v3/gicv3.mk
|
||||
|
||||
#Timer sources
|
||||
TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
|
||||
#GIC sources.
|
||||
GIC_SOURCES := plat/common/plat_gicv3.c \
|
||||
${GICV3_SOURCES} \
|
||||
|
||||
BL31_SOURCES += ${QTI_BL31_SOURCES} \
|
||||
${PSCI_SOURCES} \
|
||||
${GIC_SOURCES} \
|
||||
${TIMER_SOURCES} \
|
||||
|
||||
LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}
|
||||
|
||||
|
||||
# Override this on the command line to point to the qtiseclib library which
|
||||
# will be available in coreboot.org
|
||||
QTISECLIB_PATH ?=
|
||||
|
||||
ifeq ($(QTISECLIB_PATH),)
|
||||
# if No lib then use stub implementation for qtiseclib interface
|
||||
$(warning QTISECLIB_PATH is not provided while building, using stub implementation. \
|
||||
Please refer docs/plat/qti.rst for more details \
|
||||
THIS FIRMWARE WILL NOT BOOT!)
|
||||
BL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
|
||||
else
|
||||
# use library provided by QTISECLIB_PATH
|
||||
LDFLAGS += -L $(dir $(QTISECLIB_PATH))
|
||||
LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH)))
|
||||
endif
|
||||
|
||||
Loading…
Reference in New Issue