Fix documentation typos and misspellings
Fix some typos and misspellings in TF-A documentation. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
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@ -689,10 +689,10 @@ New Features
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- arm/common: Allow boards to specify second DRAM Base address
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- arm/common: Allow boards to specify second DRAM Base address
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and to define PLAT_ARM_TZC_FILTERS
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and to define PLAT_ARM_TZC_FILTERS
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- arm/cornstone700: Add support for mhuv2 and stack protector
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- arm/corstone700: Add support for mhuv2 and stack protector
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- arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
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- arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
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domain desciptor dynamically by leveraging fconf APIs.
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domain descriptor dynamically by leveraging fconf APIs.
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- arm/fvp: Add Cactus/Ivy Secure Partition information and use two
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- arm/fvp: Add Cactus/Ivy Secure Partition information and use two
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instances of Cactus at S-EL1
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instances of Cactus at S-EL1
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- arm/fvp: Add support to run BL32 in TDRAM and BL31 in secure DRAM
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- arm/fvp: Add support to run BL32 in TDRAM and BL31 in secure DRAM
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@ -967,7 +967,7 @@ Changed
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cpu clock, Move versal_def.h and versal_private to include directory
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cpu clock, Move versal_def.h and versal_private to include directory
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- Tools
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- Tools
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- sptool: Updated sptool to accomodate building secure partition packages.
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- sptool: Updated sptool to accommodate building secure partition packages.
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Resolved Issues
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Resolved Issues
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^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^
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@ -403,7 +403,7 @@ Common build options
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library is not supported.
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library is not supported.
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- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
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- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
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bottom, higher addresses at the top. This buid flag can be set to '1' to
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bottom, higher addresses at the top. This build flag can be set to '1' to
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invert this behavior. Lower addresses will be printed at the top and higher
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invert this behavior. Lower addresses will be printed at the top and higher
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addresses at the bottom.
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addresses at the bottom.
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@ -570,7 +570,7 @@ Common build options
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- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
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- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
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sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
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sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
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allocated in RAM discontiguous from the loaded firmware image. When set, the
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allocated in RAM discontiguous from the loaded firmware image. When set, the
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platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
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platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and
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``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
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``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
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sections are placed in RAM immediately following the loaded firmware image.
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sections are placed in RAM immediately following the loaded firmware image.
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@ -1,7 +1,7 @@
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Marvell CCU address decoding bindings
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Marvell CCU address decoding bindings
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=====================================
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=====================================
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CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The CCU node includes a description of the address decoding configuration.
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The CCU node includes a description of the address decoding configuration.
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@ -1,7 +1,7 @@
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Marvell IO WIN address decoding bindings
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Marvell IO WIN address decoding bindings
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========================================
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========================================
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IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IO WIN includes a description of the address decoding configuration.
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The IO WIN includes a description of the address decoding configuration.
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@ -1,7 +1,7 @@
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Marvell IOB address decoding bindings
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Marvell IOB address decoding bindings
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=====================================
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=====================================
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IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IOB includes a description of the address decoding configuration.
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The IOB includes a description of the address decoding configuration.
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@ -60,7 +60,7 @@ As with the previous models, the GPU and its firmware are the first entity to
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run after the SoC gets its power. The on-chip Boot ROM loads the next stage
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run after the SoC gets its power. The on-chip Boot ROM loads the next stage
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(bootcode.bin) from flash (EEPROM), which is again GPU code.
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(bootcode.bin) from flash (EEPROM), which is again GPU code.
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This part knows how to access the MMC controller and how to parse a FAT
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This part knows how to access the MMC controller and how to parse a FAT
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filesystem, so it will load further compononents and configuration files
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filesystem, so it will load further components and configuration files
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from the first FAT partition on the SD card.
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from the first FAT partition on the SD card.
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To accommodate this existing way of configuring and setting up the board,
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To accommodate this existing way of configuring and setting up the board,
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