Move BL_COHERENT_RAM_BASE/END defines to common_def.h
We have lots of duplicated defines (and comment blocks too). Move them to include/plat/common/common_def.h. While we are here, suffix the end address with _END instead of _LIMIT. The _END is a better fit to indicate the linker-derived real end address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
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ecdc898da3
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4749705355
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@ -137,4 +137,14 @@
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#define BL1_RO_DATA_END 0
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#endif /* SEPARATE_CODE_AND_RODATA */
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__)
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#endif /* __COMMON_DEF_H__ */
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@ -39,20 +39,6 @@
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#include <xlat_tables.h>
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#include "../../../bl1/bl1_private.h"
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak bl1_early_platform_setup
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#pragma weak bl1_plat_arch_setup
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@ -128,8 +114,8 @@ void arm_bl1_plat_arch_setup(void)
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BL1_RO_DATA_BASE,
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BL1_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL1_COHERENT_RAM_BASE,
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BL1_COHERENT_RAM_LIMIT
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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#ifdef AARCH32
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@ -39,18 +39,6 @@
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#include <platform_def.h>
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#include <string.h>
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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@ -242,8 +230,8 @@ void arm_bl2_plat_arch_setup(void)
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL2_COHERENT_RAM_BASE,
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BL2_COHERENT_RAM_LIMIT
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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@ -36,18 +36,6 @@
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#include <plat_arm.h>
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#include <string.h>
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL2U_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2U_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak bl2u_platform_setup
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#pragma weak bl2u_early_platform_setup
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@ -100,8 +88,8 @@ void arm_bl2u_plat_arch_setup(void)
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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,
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BL2U_COHERENT_RAM_BASE,
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BL2U_COHERENT_RAM_LIMIT
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el1(0);
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@ -41,18 +41,6 @@
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#define BL31_END (uintptr_t)(&__BL31_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
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#endif
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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@ -292,8 +280,8 @@ void arm_bl31_plat_arch_setup(void)
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el3(0);
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@ -39,19 +39,6 @@
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#define BL32_END (uintptr_t)(&__BL32_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
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#define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
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#endif
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static entry_point_info_t bl33_image_ep_info;
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/* Weak definitions may be overridden in specific ARM standard platform */
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@ -206,8 +193,8 @@ void sp_min_plat_arch_setup(void)
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL32_COHERENT_RAM_BASE,
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BL32_COHERENT_RAM_LIMIT
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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@ -37,19 +37,6 @@
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#define BL32_END (unsigned long)(&__BL32_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak tsp_early_platform_setup
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#pragma weak tsp_platform_setup
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@ -95,8 +82,8 @@ void tsp_plat_arch_setup(void)
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL32_COHERENT_RAM_BASE,
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BL32_COHERENT_RAM_LIMIT
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el1(0);
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@ -32,6 +32,7 @@
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#include <arch_helpers.h>
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#include <bl_common.h>
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#include <cci.h>
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#include <common_def.h>
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#include <console.h>
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#include <context_mgmt.h>
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#include <debug.h>
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@ -52,9 +53,6 @@
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unsigned long __RO_START__;
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unsigned long __RO_END__;
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unsigned long __COHERENT_RAM_START__;
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unsigned long __COHERENT_RAM_END__;
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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@ -64,16 +62,6 @@ unsigned long __COHERENT_RAM_END__;
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL3-1 from BL2.
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@ -323,8 +311,8 @@ void bl31_plat_arch_setup(void)
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(TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
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(BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
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BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT);
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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/* Initialize for ATF log buffer */
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if (gteearg.atf_log_buf_size != 0) {
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gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
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@ -30,6 +30,7 @@
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <common_def.h>
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#include <console.h>
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#include <debug.h>
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#include <generic_delay_timer.h>
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@ -47,9 +48,6 @@
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unsigned long __RO_START__;
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unsigned long __RO_END__;
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unsigned long __COHERENT_RAM_START__;
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unsigned long __COHERENT_RAM_END__;
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/*
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* The next 3 constants identify the extents of the code, RO data region and the
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* limit of the BL31 image. These addresses are used by the MMU setup code and
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@ -61,16 +59,6 @@ unsigned long __COHERENT_RAM_END__;
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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@ -191,10 +179,10 @@ void bl31_plat_arch_setup(void)
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plat_cci_enable();
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plat_configure_mmu_el3(BL31_RO_BASE,
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(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
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BL_COHERENT_RAM_END - BL31_RO_BASE,
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BL31_RO_BASE,
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BL31_RO_LIMIT,
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BL31_COHERENT_RAM_BASE,
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BL31_COHERENT_RAM_LIMIT);
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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}
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@ -53,11 +53,6 @@ extern unsigned long __RO_START__;
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extern unsigned long __RO_END__;
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extern unsigned long __BL31_END__;
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#if USE_COHERENT_MEM
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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#endif
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extern uint64_t tegra_bl31_phys_base;
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/*
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@ -71,18 +66,6 @@ extern uint64_t tegra_bl31_phys_base;
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
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static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
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.tzdram_size = (uint64_t)TZDRAM_SIZE
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@ -212,8 +195,8 @@ void bl31_plat_arch_setup(void)
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MT_MEMORY | MT_RO | MT_SECURE);
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#if USE_COHERENT_MEM
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coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
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coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
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mmap_add_region(coh_start, coh_start,
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coh_size,
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@ -36,18 +36,6 @@
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#include <platform_def.h>
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#include "qemu_private.h"
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/*******************************************************************************
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* Declarations of linker defined symbols which will tell us where BL1 lives
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* in Trusted RAM
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@ -98,7 +86,7 @@ void bl1_plat_arch_setup(void)
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qemu_configure_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL1_RO_BASE, BL1_RO_LIMIT,
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BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT);
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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void bl1_platform_setup(void)
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|
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@ -46,16 +46,6 @@
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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/*******************************************************************************
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* This structure represents the superset of information that is passed to
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* BL3-1, e.g. while passing control to it from BL2, bl31_params
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|
@ -216,7 +206,7 @@ void bl2_plat_arch_setup(void)
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qemu_configure_mmu_el1(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE, BL2_RO_LIMIT,
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BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT);
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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/*******************************************************************************
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|
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@ -46,16 +46,6 @@
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
|
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* refer to page-aligned addresses.
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*/
|
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
|
||||
/*
|
||||
* Placeholder variables for copying the arguments that have been passed to
|
||||
* BL3-1 from BL2.
|
||||
|
@ -105,7 +95,7 @@ void bl31_plat_arch_setup(void)
|
|||
{
|
||||
qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
|
||||
BL31_RO_BASE, BL31_RO_LIMIT,
|
||||
BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT);
|
||||
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
|
||||
}
|
||||
|
||||
static const unsigned int irq_sec_array[] = {
|
||||
|
|
|
@ -46,9 +46,6 @@
|
|||
unsigned long __RO_START__;
|
||||
unsigned long __RO_END__;
|
||||
|
||||
unsigned long __COHERENT_RAM_START__;
|
||||
unsigned long __COHERENT_RAM_END__;
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the code & RO data region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
|
@ -58,16 +55,6 @@ unsigned long __COHERENT_RAM_END__;
|
|||
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
|
||||
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
|
||||
* refer to page-aligned addresses.
|
||||
*/
|
||||
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
|
||||
static entry_point_info_t bl32_ep_info;
|
||||
static entry_point_info_t bl33_ep_info;
|
||||
|
||||
|
@ -144,9 +131,9 @@ void bl31_plat_arch_setup(void)
|
|||
plat_cci_init();
|
||||
plat_cci_enable();
|
||||
plat_configure_mmu_el3(BL31_RO_BASE,
|
||||
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
|
||||
BL_COHERENT_RAM_END - BL31_RO_BASE,
|
||||
BL31_RO_BASE,
|
||||
BL31_RO_LIMIT,
|
||||
BL31_COHERENT_RAM_BASE,
|
||||
BL31_COHERENT_RAM_LIMIT);
|
||||
BL_COHERENT_RAM_BASE,
|
||||
BL_COHERENT_RAM_END);
|
||||
}
|
||||
|
|
|
@ -40,16 +40,6 @@
|
|||
|
||||
#define BL31_END (unsigned long)(&__BL31_END__)
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
|
||||
* refer to page-aligned addresses.
|
||||
*/
|
||||
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
|
||||
static entry_point_info_t bl32_image_ep_info;
|
||||
static entry_point_info_t bl33_image_ep_info;
|
||||
|
||||
|
@ -163,7 +153,7 @@ void bl31_plat_arch_setup(void)
|
|||
BL_CODE_END,
|
||||
BL_RO_DATA_BASE,
|
||||
BL_RO_DATA_END,
|
||||
BL31_COHERENT_RAM_BASE,
|
||||
BL31_COHERENT_RAM_LIMIT);
|
||||
BL_COHERENT_RAM_BASE,
|
||||
BL_COHERENT_RAM_END);
|
||||
enable_mmu_el3(0);
|
||||
}
|
||||
|
|
|
@ -37,16 +37,6 @@
|
|||
|
||||
#define BL32_END (unsigned long)(&__BL32_END__)
|
||||
|
||||
/*
|
||||
* The next 2 constants identify the extents of the coherent memory region.
|
||||
* These addresses are used by the MMU setup code and therefore they must be
|
||||
* page-aligned. It is the responsibility of the linker script to ensure that
|
||||
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
|
||||
* page-aligned addresses.
|
||||
*/
|
||||
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
|
||||
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the UART
|
||||
******************************************************************************/
|
||||
|
@ -84,8 +74,8 @@ void tsp_plat_arch_setup(void)
|
|||
BL_CODE_END,
|
||||
BL_RO_DATA_BASE,
|
||||
BL_RO_DATA_END,
|
||||
BL32_COHERENT_RAM_BASE,
|
||||
BL32_COHERENT_RAM_LIMIT
|
||||
BL_COHERENT_RAM_BASE,
|
||||
BL_COHERENT_RAM_END
|
||||
);
|
||||
enable_mmu_el1(0);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue