Merge changes from topic "x2_errata" into integration
* changes: fix(errata): workaround for Cortex-A710 erratum 2136059 fix(errata): workaround for Cortex-A710 erratum 2267065 fix(errata): workaround for Cortex-X2 erratum 2216384 fix(errata): workaround for Cortex-X2 errata 2081180 fix(errata): workaround for Cortex-X2 errata 2017096
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
47909f9d11
|
|
@ -409,6 +409,14 @@ For Cortex-A710, the following errata build flags are defined :
|
|||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is fixed in r2p1.
|
||||
|
||||
For Neoverse N2, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
|
||||
|
|
@ -454,6 +462,18 @@ For Cortex-X2, the following errata build flags are defined :
|
|||
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
|
||||
CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
|
||||
|
||||
- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU, it is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU, it is fixed in r2p1.
|
||||
|
||||
- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
|
||||
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU, it is fixed in r2p1.
|
||||
|
||||
DSU Errata Workarounds
|
||||
----------------------
|
||||
|
||||
|
|
|
|||
|
|
@ -26,12 +26,14 @@
|
|||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
||||
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register 2 specific definitions
|
||||
|
|
@ -33,5 +34,14 @@
|
|||
* CPU Auxiliary Control Register 5 definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Implementation Specific Selected Instruction registers
|
||||
******************************************************************************/
|
||||
#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
|
||||
#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
|
||||
#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
|
||||
#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
|
||||
|
||||
#endif /* CORTEX_X2_H */
|
||||
|
|
|
|||
|
|
@ -216,6 +216,65 @@ func check_errata_2058056
|
|||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2058056
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for Cortex-A710 Erratum 2267065.
|
||||
* This applies to revisions r0p0, r1p0 and r2p0.
|
||||
* It is fixed in r2p1.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x1, x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_a710_2267065_wa
|
||||
/* Compare x0 against revision r2p0 */
|
||||
mov x17, x30
|
||||
bl check_errata_2267065
|
||||
cbz x0, 1f
|
||||
|
||||
/* Apply instruction patching sequence */
|
||||
mrs x1, CORTEX_A710_CPUACTLR_EL1
|
||||
orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
|
||||
msr CORTEX_A710_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a710_2267065_wa
|
||||
|
||||
func check_errata_2267065
|
||||
/* Applies to r0p0, r1p0 and r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2267065
|
||||
|
||||
/* ---------------------------------------------------------------
|
||||
* Errata Workaround for Cortex-A710 Erratum 2136059.
|
||||
* This applies to revision r0p0, r1p0 and r2p0.
|
||||
* It is fixed in r2p1.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* ---------------------------------------------------------------
|
||||
*/
|
||||
func errata_a710_2136059_wa
|
||||
/* Compare x0 against revision r2p0 */
|
||||
mov x17, x30
|
||||
bl check_errata_2136059
|
||||
cbz x0, 1f
|
||||
|
||||
/* Apply the workaround */
|
||||
mrs x1, CORTEX_A710_CPUACTLR5_EL1
|
||||
orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44
|
||||
msr CORTEX_A710_CPUACTLR5_EL1, x1
|
||||
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a710_2136059_wa
|
||||
|
||||
func check_errata_2136059
|
||||
/* Applies to r0p0, r1p0 and r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2136059
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ----------------------------------------------------
|
||||
|
|
@ -252,6 +311,8 @@ func cortex_a710_errata_report
|
|||
report_errata ERRATA_A710_2017096, cortex_a710, 2017096
|
||||
report_errata ERRATA_A710_2083908, cortex_a710, 2083908
|
||||
report_errata ERRATA_A710_2058056, cortex_a710, 2058056
|
||||
report_errata ERRATA_A710_2267065, cortex_a710, 2267065
|
||||
report_errata ERRATA_A710_2136059, cortex_a710, 2136059
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
|
|
@ -296,6 +357,17 @@ func cortex_a710_reset_func
|
|||
mov x0, x18
|
||||
bl errata_a710_2058056_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A710_2267065
|
||||
mov x0, x18
|
||||
bl errata_a710_2267065_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A710_2136059
|
||||
mov x0, x18
|
||||
bl errata_a710_2136059_wa
|
||||
#endif
|
||||
|
||||
isb
|
||||
ret x19
|
||||
endfunc cortex_a710_reset_func
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -113,6 +113,115 @@ func check_errata_2083908
|
|||
b cpu_rev_var_range
|
||||
endfunc check_errata_2083908
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for Cortex-X2 Errata 2017096.
|
||||
* This applies only to revisions r0p0, r1p0 and r2p0
|
||||
* and is fixed in r2p1.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0, x1, x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_x2_2017096_wa
|
||||
/* Compare x0 against revision r0p0 to r2p0 */
|
||||
mov x17, x30
|
||||
bl check_errata_2017096
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_X2_CPUECTLR_EL1
|
||||
orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
|
||||
msr CORTEX_X2_CPUECTLR_EL1, x1
|
||||
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_x2_2017096_wa
|
||||
|
||||
func check_errata_2017096
|
||||
/* Applies to r0p0, r1p0, r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2017096
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for Cortex-X2 Errata 2081180.
|
||||
* This applies to revision r0p0, r1p0 and r2p0
|
||||
* and is fixed in r2p1.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0, x1, x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_x2_2081180_wa
|
||||
/* Check revision. */
|
||||
mov x17, x30
|
||||
bl check_errata_2081180
|
||||
cbz x0, 1f
|
||||
|
||||
/* Apply instruction patching sequence */
|
||||
ldr x0, =0x3
|
||||
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
|
||||
ldr x0, =0xF3A08002
|
||||
msr CORTEX_X2_IMP_CPUPOR_EL3, x0
|
||||
ldr x0, =0xFFF0F7FE
|
||||
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
|
||||
ldr x0, =0x10002001003FF
|
||||
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
|
||||
ldr x0, =0x4
|
||||
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
|
||||
ldr x0, =0xBF200000
|
||||
msr CORTEX_X2_IMP_CPUPOR_EL3, x0
|
||||
ldr x0, =0xFFEF0000
|
||||
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
|
||||
ldr x0, =0x10002001003F3
|
||||
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_x2_2081180_wa
|
||||
|
||||
func check_errata_2081180
|
||||
/* Applies to r0p0, r1p0 and r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2081180
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for Cortex X2 Errata 2216384.
|
||||
* This applies to revisions r0p0, r1p0, and r2p0
|
||||
* and is fixed in r2p1.
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0, x1, x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_x2_2216384_wa
|
||||
/* Check workaround compatibility. */
|
||||
mov x17, x30
|
||||
bl check_errata_2216384
|
||||
cbz x0, 1f
|
||||
|
||||
mrs x1, CORTEX_X2_CPUACTLR5_EL1
|
||||
orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
|
||||
msr CORTEX_X2_CPUACTLR5_EL1, x1
|
||||
|
||||
/* Apply instruction patching sequence */
|
||||
ldr x0, =0x5
|
||||
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
|
||||
ldr x0, =0x10F600E000
|
||||
msr CORTEX_X2_IMP_CPUPOR_EL3, x0
|
||||
ldr x0, =0x10FF80E000
|
||||
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
|
||||
ldr x0, =0x80000000003FF
|
||||
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
|
||||
isb
|
||||
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_x2_2216384_wa
|
||||
|
||||
func check_errata_2216384
|
||||
/* Applies to r0p0 - r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2216384
|
||||
/* ----------------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ----------------------------------------------------
|
||||
|
|
@ -146,6 +255,9 @@ func cortex_x2_errata_report
|
|||
report_errata ERRATA_X2_2002765, cortex_x2, 2002765
|
||||
report_errata ERRATA_X2_2058056, cortex_x2, 2058056
|
||||
report_errata ERRATA_X2_2083908, cortex_x2, 2083908
|
||||
report_errata ERRATA_X2_2017096, cortex_x2, 2017096
|
||||
report_errata ERRATA_X2_2081180, cortex_x2, 2081180
|
||||
report_errata ERRATA_X2_2216384, cortex_x2, 2216384
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
|
|
@ -178,6 +290,21 @@ func cortex_x2_reset_func
|
|||
bl errata_cortex_x2_2083908_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_X2_2017096
|
||||
mov x0, x18
|
||||
bl errata_x2_2017096_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_X2_2081180
|
||||
mov x0, x18
|
||||
bl errata_x2_2081180_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_X2_2216384
|
||||
mov x0, x18
|
||||
bl errata_x2_2216384_wa
|
||||
#endif
|
||||
|
||||
ret x19
|
||||
endfunc cortex_x2_reset_func
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -495,17 +495,40 @@ ERRATA_A710_2055002 ?=0
|
|||
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
|
||||
ERRATA_A710_2017096 ?=0
|
||||
|
||||
# Flag to apply erratum 2267065 workaround during reset. This erratum applies
|
||||
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
|
||||
ERRATA_A710_2267065 ?=0
|
||||
|
||||
# Flag to apply erratum 2136059 workaround during reset. This erratum applies
|
||||
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
|
||||
ERRATA_A710_2136059 ?=0
|
||||
|
||||
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
|
||||
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
|
||||
ERRATA_X2_2002765 ?=0
|
||||
ERRATA_X2_2002765 ?=0
|
||||
|
||||
# Flag to apply erratum 2058056 workaround during reset. This erratum applies
|
||||
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
|
||||
ERRATA_X2_2058056 ?=0
|
||||
ERRATA_X2_2058056 ?=0
|
||||
|
||||
# Flag to apply erratum 2083908 workaround during reset. This erratum applies
|
||||
# to revision r2p0 of the Cortex-X2 cpu and is still open.
|
||||
ERRATA_X2_2083908 ?=0
|
||||
ERRATA_X2_2083908 ?=0
|
||||
|
||||
# Flag to apply erratum 2017096 workaround during reset. This erratum applies
|
||||
# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
|
||||
# r2p1.
|
||||
ERRATA_X2_2017096 ?=0
|
||||
|
||||
# Flag to apply erratum 2081180 workaround during reset. This erratum applies
|
||||
# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
|
||||
# r2p1.
|
||||
ERRATA_X2_2081180 ?=0
|
||||
|
||||
# Flag to apply erratum 2216384 workaround during reset. This erratum applies
|
||||
# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
|
||||
# r2p1.
|
||||
ERRATA_X2_2216384 ?=0
|
||||
|
||||
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
|
||||
# Applying the workaround results in higher DSU power consumption on idle.
|
||||
|
|
@ -932,6 +955,14 @@ $(eval $(call add_define,ERRATA_A710_2055002))
|
|||
$(eval $(call assert_boolean,ERRATA_A710_2017096))
|
||||
$(eval $(call add_define,ERRATA_A710_2017096))
|
||||
|
||||
# Process ERRATA_A710_2267065 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A710_2267065))
|
||||
$(eval $(call add_define,ERRATA_A710_2267065))
|
||||
|
||||
# Process ERRATA_A710_2136059 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A710_2136059))
|
||||
$(eval $(call add_define,ERRATA_A710_2136059))
|
||||
|
||||
# Process ERRATA_X2_2002765 flag
|
||||
$(eval $(call assert_boolean,ERRATA_X2_2002765))
|
||||
$(eval $(call add_define,ERRATA_X2_2002765))
|
||||
|
|
@ -944,6 +975,18 @@ $(eval $(call add_define,ERRATA_X2_2058056))
|
|||
$(eval $(call assert_boolean,ERRATA_X2_2083908))
|
||||
$(eval $(call add_define,ERRATA_X2_2083908))
|
||||
|
||||
# Process ERRATA_X2_2017096 flag
|
||||
$(eval $(call assert_boolean,ERRATA_X2_2017096))
|
||||
$(eval $(call add_define,ERRATA_X2_2017096))
|
||||
|
||||
# Process ERRATA_X2_2081180 flag
|
||||
$(eval $(call assert_boolean,ERRATA_X2_2081180))
|
||||
$(eval $(call add_define,ERRATA_X2_2081180))
|
||||
|
||||
# Process ERRATA_X2_2216384 flag
|
||||
$(eval $(call assert_boolean,ERRATA_X2_2216384))
|
||||
$(eval $(call add_define,ERRATA_X2_2216384))
|
||||
|
||||
# Process ERRATA_DSU_798953 flag
|
||||
$(eval $(call assert_boolean,ERRATA_DSU_798953))
|
||||
$(eval $(call add_define,ERRATA_DSU_798953))
|
||||
|
|
|
|||
Loading…
Reference in New Issue