Merge pull request #910 from dp-arm/dp/AArch32-juno-port
Add AArch32 support for Juno
This commit is contained in:
davidcunado-arm
GitHub
commit
484acce376
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@ -134,4 +134,37 @@
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.space SPINLOCK_ASM_SIZE
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.endm
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/*
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* Helper macro to OR the bottom 32 bits of `_val` into `_reg_l`
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* and the top 32 bits of `_val` into `_reg_h`. If either the bottom
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* or top word of `_val` is zero, the corresponding OR operation
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* is skipped.
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*/
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.macro orr64_imm _reg_l, _reg_h, _val
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.if (\_val >> 32)
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orr \_reg_h, \_reg_h, #(\_val >> 32)
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.endif
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.if (\_val & 0xffffffff)
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orr \_reg_l, \_reg_l, #(\_val & 0xffffffff)
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.endif
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.endm
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/*
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* Helper macro to bitwise-clear bits in `_reg_l` and
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* `_reg_h` given a 64 bit immediate `_val`. The set bits
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* in the bottom word of `_val` dictate which bits from
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* `_reg_l` should be cleared. Similarly, the set bits in
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* the top word of `_val` dictate which bits from `_reg_h`
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* should be cleared. If either the bottom or top word of
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* `_val` is zero, the corresponding BIC operation is skipped.
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*/
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.macro bic64_imm _reg_l, _reg_h, _val
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.if (\_val >> 32)
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bic \_reg_h, \_reg_h, #(\_val >> 32)
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.endif
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.if (\_val & 0xffffffff)
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bic \_reg_l, \_reg_l, #(\_val & 0xffffffff)
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.endif
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.endm
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#endif /* __ASM_MACROS_S__ */
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@ -394,12 +394,14 @@
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#define HCR p15, 4, c1, c1, 0
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#define HCPTR p15, 4, c1, c1, 2
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#define CNTHCTL p15, 4, c14, c1, 0
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#define CNTKCTL p15, 0, c14, c1, 0
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#define VPIDR p15, 4, c0, c0, 0
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#define VMPIDR p15, 4, c0, c0, 5
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#define ISR p15, 0, c12, c1, 0
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#define CLIDR p15, 1, c0, c0, 1
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#define CSSELR p15, 2, c0, c0, 0
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#define CCSIDR p15, 1, c0, c0, 0
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#define DBGOSDLR p14, 0, c1, c3, 4
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/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define HDCR p15, 4, c1, c1, 1
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@ -209,6 +209,8 @@ DEFINE_SYSOP_FUNC(wfe)
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DEFINE_SYSOP_FUNC(sev)
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DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, st)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
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@ -261,6 +261,16 @@
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#define DISABLE_ALL_EXCEPTIONS \
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(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
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/*
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* RMR_EL3 definitions
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*/
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#define RMR_EL3_RR_BIT (1 << 1)
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#define RMR_EL3_AA64_BIT (1 << 0)
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/*
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* HI-VECTOR address for AArch32 state
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*/
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#define HI_VECTOR_BASE (0xFFFF0000)
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/*
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* TCR defintions
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@ -0,0 +1,92 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
|
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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||||
*
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* Neither the name of ARM nor the names of its contributors may be used
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||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
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*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CORTEX_A53_H__
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#define __CORTEX_A53_H__
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/* Cortex-A53 midr for revision 0 */
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#define CORTEX_A53_MIDR 0x410FD030
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 0x1
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#define RETENTION_ENTRY_TICKS_8 0x2
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#define RETENTION_ENTRY_TICKS_32 0x3
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#define RETENTION_ENTRY_TICKS_64 0x4
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#define RETENTION_ENTRY_TICKS_128 0x5
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#define RETENTION_ENTRY_TICKS_256 0x6
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#define RETENTION_ENTRY_TICKS_512 0x7
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CPUECTLR p15, 1, c15 /* Instruction def. */
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#define CPUECTLR_SMP_BIT (1 << 6)
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#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
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#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
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#define CPUECTLR_FPU_RET_CTRL_SHIFT 3
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#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CPUMERRSR p15, 2, c15 /* Instruction def. */
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CPUACTLR p15, 0, c15 /* Instruction def. */
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#define CPUACTLR_DTAH (1 << 24)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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#define L2ACTLR p15, 1, c15, c0, 0 /* Instruction def. */
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#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
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#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */
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#define L2ECTLR_RET_CTRL_SHIFT 0
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#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define L2MERRSR p15, 3, c15 /* Instruction def. */
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#endif /* __CORTEX_A53_H__ */
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@ -0,0 +1,103 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
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||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef __CORTEX_A57_H__
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#define __CORTEX_A57_H__
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR 0x410FD070
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 0x1
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#define RETENTION_ENTRY_TICKS_8 0x2
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#define RETENTION_ENTRY_TICKS_32 0x3
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#define RETENTION_ENTRY_TICKS_64 0x4
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#define RETENTION_ENTRY_TICKS_128 0x5
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#define RETENTION_ENTRY_TICKS_256 0x6
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#define RETENTION_ENTRY_TICKS_512 0x7
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CPUECTLR p15, 1, c15 /* Instruction def. */
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#define CPUECTLR_SMP_BIT (1 << 6)
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#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
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#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
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#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
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#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
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#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CPUMERRSR p15, 2, c15 /* Instruction def. */
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CPUACTLR p15, 0, c15 /* Instruction def. */
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#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59)
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#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
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#define CPUACTLR_DIS_OVERREAD (1 << 52)
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#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
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#define CPUACTLR_DCC_AS_DCCI (1 << 44)
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#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38)
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#define CPUACTLR_DIS_STREAMING (3 << 27)
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#define CPUACTLR_DIS_L1_STREAMING (3 << 25)
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#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */
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#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */
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#define L2ECTLR_RET_CTRL_SHIFT 0
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#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define L2MERRSR p15, 3, c15 /* Instruction def. */
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#endif /* __CORTEX_A57_H__ */
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@ -0,0 +1,78 @@
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/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CORTEX_A72_H__
|
||||
#define __CORTEX_A72_H__
|
||||
|
||||
/* Cortex-A72 midr for revision 0 */
|
||||
#define CORTEX_A72_MIDR 0x410FD080
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Extended Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUECTLR p15, 1, c15 /* Instruction def. */
|
||||
|
||||
#define CPUECTLR_SMP_BIT (1 << 6)
|
||||
#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
|
||||
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
|
||||
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUMERRSR p15, 2, c15 /* Instruction def. */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CPUACTLR p15, 0, c15 /* Instruction def. */
|
||||
|
||||
#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
|
||||
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
|
||||
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */
|
||||
|
||||
#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
|
||||
#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
|
||||
|
||||
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
|
||||
#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1
|
||||
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
|
||||
|
||||
/*******************************************************************************
|
||||
* L2 Memory Error Syndrome register specific definitions.
|
||||
******************************************************************************/
|
||||
#define L2MERRSR p15, 3, c15 /* Instruction def. */
|
||||
|
||||
#endif /* __CORTEX_A72_H__ */
|
||||
|
|
@ -81,7 +81,7 @@ void arm_setup_page_tables(uintptr_t total_base,
|
|||
#else
|
||||
|
||||
/*
|
||||
* Empty macros for all other BL stages other than BL31
|
||||
* Empty macros for all other BL stages other than BL31 and BL32
|
||||
*/
|
||||
#define ARM_INSTANTIATE_LOCK
|
||||
#define arm_lock_init()
|
||||
|
|
@ -157,6 +157,7 @@ void arm_bl2_platform_setup(void);
|
|||
void arm_bl2_plat_arch_setup(void);
|
||||
uint32_t arm_get_spsr_for_bl32_entry(void);
|
||||
uint32_t arm_get_spsr_for_bl33_entry(void);
|
||||
int arm_bl2_handle_post_image_load(unsigned int image_id);
|
||||
|
||||
/* BL2U utility functions */
|
||||
void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
|
||||
|
|
|
|||
|
|
@ -96,9 +96,16 @@
|
|||
/*
|
||||
* Required platform porting definitions common to all ARM CSS SoCs
|
||||
*/
|
||||
|
||||
#if JUNO_AARCH32_EL3_RUNTIME
|
||||
/*
|
||||
* Following change is required to initialize TZC
|
||||
* for enabling access to the HI_VECTOR (0xFFFF0000)
|
||||
* location needed for JUNO AARCH32 support.
|
||||
*/
|
||||
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000)
|
||||
#else
|
||||
/* 2MB used for SCP DDR retraining */
|
||||
#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __SOC_CSS_DEF_H__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include <cortex_a53.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <debug.h>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable intra-cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a53_disable_smp
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
bic64_imm r0, r1, CPUECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
isb
|
||||
dsb sy
|
||||
bx lr
|
||||
endfunc cortex_a53_disable_smp
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A53.
|
||||
* -------------------------------------------------
|
||||
*/
|
||||
func cortex_a53_reset_func
|
||||
/* ---------------------------------------------
|
||||
* Enable the SMP bit.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
orr64_imm r0, r1, CPUECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc cortex_a53_reset_func
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* The CPU Ops core power down function for Cortex-A53.
|
||||
* ----------------------------------------------------
|
||||
*/
|
||||
func cortex_a53_core_pwr_dwn
|
||||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L1 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level1
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Come out of intra cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
pop {r12, lr}
|
||||
b cortex_a53_disable_smp
|
||||
endfunc cortex_a53_core_pwr_dwn
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* The CPU Ops cluster power down function for Cortex-A53.
|
||||
* Clobbers: r0-r3
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
func cortex_a53_cluster_pwr_dwn
|
||||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L1 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level1
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the optional ACP.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl plat_disable_acp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L2 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level2
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Come out of intra cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
pop {r12, lr}
|
||||
b cortex_a53_disable_smp
|
||||
endfunc cortex_a53_cluster_pwr_dwn
|
||||
|
||||
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
|
||||
cortex_a53_reset_func, \
|
||||
cortex_a53_core_pwr_dwn, \
|
||||
cortex_a53_cluster_pwr_dwn
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include <cortex_a57.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <debug.h>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable intra-cluster coherency
|
||||
* Clobbers: r0-r1
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a57_disable_smp
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
bic64_imm r0, r1, CPUECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
bx lr
|
||||
endfunc cortex_a57_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable all types of L2 prefetches.
|
||||
* Clobbers: r0-r2
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a57_disable_l2_prefetch
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
|
||||
bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \
|
||||
CPUECTLR_L2_DPFTCH_DIST_MASK)
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
isb
|
||||
dsb ish
|
||||
bx lr
|
||||
endfunc cortex_a57_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable debug interfaces
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a57_disable_ext_debug
|
||||
mov r0, #1
|
||||
stcopr r0, DBGOSDLR
|
||||
isb
|
||||
dsb sy
|
||||
bx lr
|
||||
endfunc cortex_a57_disable_ext_debug
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A57.
|
||||
* -------------------------------------------------
|
||||
*/
|
||||
func cortex_a57_reset_func
|
||||
/* ---------------------------------------------
|
||||
* Enable the SMP bit.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
orr64_imm r0, r1, CPUECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc cortex_a57_reset_func
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* The CPU Ops core power down function for Cortex-A57.
|
||||
* ----------------------------------------------------
|
||||
*/
|
||||
func cortex_a57_core_pwr_dwn
|
||||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the L2 prefetches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a57_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L1 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level1
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Come out of intra cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a57_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Force the debug interfaces to be quiescent
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
pop {r12, lr}
|
||||
b cortex_a57_disable_ext_debug
|
||||
endfunc cortex_a57_core_pwr_dwn
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* The CPU Ops cluster power down function for Cortex-A57.
|
||||
* Clobbers: r0-r3
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
func cortex_a57_cluster_pwr_dwn
|
||||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the L2 prefetches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a57_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L1 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level1
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the optional ACP.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl plat_disable_acp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L2 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level2
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Come out of intra cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a57_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Force the debug interfaces to be quiescent
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
pop {r12, lr}
|
||||
b cortex_a57_disable_ext_debug
|
||||
endfunc cortex_a57_cluster_pwr_dwn
|
||||
|
||||
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
|
||||
cortex_a57_reset_func, \
|
||||
cortex_a57_core_pwr_dwn, \
|
||||
cortex_a57_cluster_pwr_dwn
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <assert_macros.S>
|
||||
#include <cortex_a72.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <debug.h>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable all types of L2 prefetches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a72_disable_l2_prefetch
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
|
||||
bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \
|
||||
CPUECTLR_L2_DPFTCH_DIST_MASK)
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc cortex_a72_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the load-store hardware prefetcher.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a72_disable_hw_prefetcher
|
||||
ldcopr16 r0, r1, CPUACTLR
|
||||
orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
|
||||
stcopr16 r0, r1, CPUACTLR
|
||||
isb
|
||||
dsb ish
|
||||
bx lr
|
||||
endfunc cortex_a72_disable_hw_prefetcher
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable intra-cluster coherency
|
||||
* Clobbers: r0-r1
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a72_disable_smp
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
bic64_imm r0, r1, CPUECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
bx lr
|
||||
endfunc cortex_a72_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable debug interfaces
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func cortex_a72_disable_ext_debug
|
||||
mov r0, #1
|
||||
stcopr r0, DBGOSDLR
|
||||
isb
|
||||
dsb sy
|
||||
bx lr
|
||||
endfunc cortex_a72_disable_ext_debug
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A72.
|
||||
* -------------------------------------------------
|
||||
*/
|
||||
func cortex_a72_reset_func
|
||||
/* ---------------------------------------------
|
||||
* Enable the SMP bit.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
ldcopr16 r0, r1, CPUECTLR
|
||||
orr64_imm r0, r1, CPUECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CPUECTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc cortex_a72_reset_func
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* The CPU Ops core power down function for Cortex-A72.
|
||||
* ----------------------------------------------------
|
||||
*/
|
||||
func cortex_a72_core_pwr_dwn
|
||||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the L2 prefetches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a72_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the load-store hardware prefetcher.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a72_disable_hw_prefetcher
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Flush L1 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level1
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Come out of intra cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a72_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Force the debug interfaces to be quiescent
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
pop {r12, lr}
|
||||
b cortex_a72_disable_ext_debug
|
||||
endfunc cortex_a72_core_pwr_dwn
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* The CPU Ops cluster power down function for Cortex-A72.
|
||||
* -------------------------------------------------------
|
||||
*/
|
||||
func cortex_a72_cluster_pwr_dwn
|
||||
push {r12, lr}
|
||||
|
||||
/* Assert if cache is enabled */
|
||||
#if ASM_ASSERTION
|
||||
ldcopr r0, SCTLR
|
||||
tst r0, #SCTLR_C_BIT
|
||||
ASM_ASSERT(eq)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the L2 prefetches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a72_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the load-store hardware prefetcher.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a72_disable_hw_prefetcher
|
||||
|
||||
#if !SKIP_A72_L1_FLUSH_PWR_DWN
|
||||
/* ---------------------------------------------
|
||||
* Flush L1 caches.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level1
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the optional ACP.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl plat_disable_acp
|
||||
|
||||
/* -------------------------------------------------
|
||||
* Flush the L2 caches.
|
||||
* -------------------------------------------------
|
||||
*/
|
||||
mov r0, #DC_OP_CISW
|
||||
bl dcsw_op_level2
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Come out of intra cluster coherency
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl cortex_a72_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Force the debug interfaces to be quiescent
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
pop {r12, lr}
|
||||
b cortex_a72_disable_ext_debug
|
||||
endfunc cortex_a72_cluster_pwr_dwn
|
||||
|
||||
declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
|
||||
cortex_a72_reset_func, \
|
||||
cortex_a72_core_pwr_dwn, \
|
||||
cortex_a72_cluster_pwr_dwn
|
||||
|
|
@ -79,6 +79,9 @@ const mmap_region_t plat_arm_mmap[] = {
|
|||
#endif
|
||||
#ifdef IMAGE_BL32
|
||||
const mmap_region_t plat_arm_mmap[] = {
|
||||
#ifdef AARCH32
|
||||
ARM_MAP_SHARED_RAM,
|
||||
#endif
|
||||
V2M_MAP_IOFPGA,
|
||||
CSS_MAP_DEVICE,
|
||||
SOC_CSS_MAP_DEVICE,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <bl_common.h>
|
||||
#include <cortex_a53.h>
|
||||
#include <cortex_a57.h>
|
||||
#include <cortex_a72.h>
|
||||
#include <v2m_def.h>
|
||||
#include "../juno_def.h"
|
||||
|
||||
|
||||
.globl plat_reset_handler
|
||||
.globl plat_arm_calc_core_pos
|
||||
|
||||
#define JUNO_REVISION(rev) REV_JUNO_R##rev
|
||||
#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
|
||||
#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \
|
||||
jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision)
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Helper macro to jump to the given handler if the board revision
|
||||
* matches.
|
||||
* Expects the Juno board revision in x0.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
.macro jump_to_handler _revision, _handler
|
||||
cmp r0, #\_revision
|
||||
beq \_handler
|
||||
.endm
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Helper macro that reads the part number of the current CPU and jumps
|
||||
* to the given label if it matches the CPU MIDR provided.
|
||||
*
|
||||
* Clobbers r0.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
.macro jump_if_cpu_midr _cpu_midr, _label
|
||||
ldcopr r0, MIDR
|
||||
ubfx r0, r0, #MIDR_PN_SHIFT, #12
|
||||
ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
|
||||
cmp r0, r1
|
||||
beq \_label
|
||||
.endm
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Platform reset handler for Juno R0.
|
||||
*
|
||||
* Juno R0 has the following topology:
|
||||
* - Quad core Cortex-A53 processor cluster;
|
||||
* - Dual core Cortex-A57 processor cluster.
|
||||
*
|
||||
* This handler does the following:
|
||||
* - Implement workaround for defect id 831273 by enabling an event
|
||||
* stream every 65536 cycles.
|
||||
* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
|
||||
* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
func JUNO_HANDLER(0)
|
||||
/* --------------------------------------------------------------------
|
||||
* Enable the event stream every 65536 cycles
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #(0xf << EVNTI_SHIFT)
|
||||
orr r0, r0, #EVNTEN_BIT
|
||||
stcopr r0, CNTKCTL
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Nothing else to do on Cortex-A53.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
jump_if_cpu_midr CORTEX_A53_MIDR, 1f
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Cortex-A57 specific settings
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
|
||||
stcopr r0, L2CTLR
|
||||
1:
|
||||
isb
|
||||
bx lr
|
||||
endfunc JUNO_HANDLER(0)
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Platform reset handler for Juno R1.
|
||||
*
|
||||
* Juno R1 has the following topology:
|
||||
* - Quad core Cortex-A53 processor cluster;
|
||||
* - Dual core Cortex-A57 processor cluster.
|
||||
*
|
||||
* This handler does the following:
|
||||
* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
|
||||
*
|
||||
* Note that:
|
||||
* - The default value for the L2 Tag RAM latency for Cortex-A57 is
|
||||
* suitable.
|
||||
* - Defect #831273 doesn't affect Juno R1.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
func JUNO_HANDLER(1)
|
||||
/* --------------------------------------------------------------------
|
||||
* Nothing to do on Cortex-A53.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
jump_if_cpu_midr CORTEX_A57_MIDR, A57
|
||||
bx lr
|
||||
|
||||
A57:
|
||||
/* --------------------------------------------------------------------
|
||||
* Cortex-A57 specific settings
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
|
||||
stcopr r0, L2CTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc JUNO_HANDLER(1)
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Platform reset handler for Juno R2.
|
||||
*
|
||||
* Juno R2 has the following topology:
|
||||
* - Quad core Cortex-A53 processor cluster;
|
||||
* - Dual core Cortex-A72 processor cluster.
|
||||
*
|
||||
* This handler does the following:
|
||||
* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
|
||||
* - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
|
||||
*
|
||||
* Note that:
|
||||
* - Defect #831273 doesn't affect Juno R2.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
func JUNO_HANDLER(2)
|
||||
/* --------------------------------------------------------------------
|
||||
* Nothing to do on Cortex-A53.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
jump_if_cpu_midr CORTEX_A72_MIDR, A72
|
||||
bx lr
|
||||
|
||||
A72:
|
||||
/* --------------------------------------------------------------------
|
||||
* Cortex-A72 specific settings
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
|
||||
stcopr r0, L2CTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc JUNO_HANDLER(2)
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* void plat_reset_handler(void);
|
||||
*
|
||||
* Determine the Juno board revision and call the appropriate reset
|
||||
* handler.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
func plat_reset_handler
|
||||
/* Read the V2M SYS_ID register */
|
||||
ldr r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID)
|
||||
ldr r1, [r0]
|
||||
/* Extract board revision from the SYS_ID */
|
||||
ubfx r0, r1, #V2M_SYS_ID_REV_SHIFT, #4
|
||||
|
||||
JUMP_TO_HANDLER_IF_JUNO_R(0)
|
||||
JUMP_TO_HANDLER_IF_JUNO_R(1)
|
||||
JUMP_TO_HANDLER_IF_JUNO_R(2)
|
||||
|
||||
/* Board revision is not supported */
|
||||
no_ret plat_panic_handler
|
||||
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
||||
* Helper function to calculate the core position.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_arm_calc_core_pos
|
||||
b css_calc_core_pos_swap_cluster
|
||||
endfunc plat_arm_calc_core_pos
|
||||
|
|
@ -34,12 +34,18 @@
|
|||
#include <cortex_a53.h>
|
||||
#include <cortex_a57.h>
|
||||
#include <cortex_a72.h>
|
||||
#include <cpu_macros.S>
|
||||
#include <css_def.h>
|
||||
#include <v2m_def.h>
|
||||
#include "../juno_def.h"
|
||||
|
||||
|
||||
.globl plat_reset_handler
|
||||
.globl plat_arm_calc_core_pos
|
||||
#if JUNO_AARCH32_EL3_RUNTIME
|
||||
.globl plat_get_my_entrypoint
|
||||
.globl juno_reset_to_aarch32_state
|
||||
#endif
|
||||
|
||||
#define JUNO_REVISION(rev) REV_JUNO_R##rev
|
||||
#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
|
||||
|
|
@ -205,6 +211,20 @@ func plat_reset_handler
|
|||
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void juno_do_reset_to_aarch32_state(void);
|
||||
*
|
||||
* Request warm reset to AArch32 mode.
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func juno_do_reset_to_aarch32_state
|
||||
mov x0, #RMR_EL3_RR_BIT
|
||||
dsb sy
|
||||
msr rmr_el3, x0
|
||||
isb
|
||||
wfi
|
||||
endfunc juno_do_reset_to_aarch32_state
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
|
||||
* Helper function to calculate the core position.
|
||||
|
|
@ -213,3 +233,77 @@ endfunc plat_reset_handler
|
|||
func plat_arm_calc_core_pos
|
||||
b css_calc_core_pos_swap_cluster
|
||||
endfunc plat_arm_calc_core_pos
|
||||
|
||||
#if JUNO_AARCH32_EL3_RUNTIME
|
||||
/* ---------------------------------------------------------------------
|
||||
* uintptr_t plat_get_my_entrypoint (void);
|
||||
*
|
||||
* Main job of this routine is to distinguish between a cold and a warm
|
||||
* boot. On JUNO platform, this distinction is based on the contents of
|
||||
* the Trusted Mailbox. It is initialised to zero by the SCP before the
|
||||
* AP cores are released from reset. Therefore, a zero mailbox means
|
||||
* it's a cold reset. If it is a warm boot then a request to reset to
|
||||
* AArch32 state is issued. This is the only way to reset to AArch32
|
||||
* in EL3 on Juno. A trampoline located at the high vector address
|
||||
* has already been prepared by BL1.
|
||||
*
|
||||
* This functions returns the contents of the mailbox, i.e.:
|
||||
* - 0 for a cold boot;
|
||||
* - request warm reset in AArch32 state for warm boot case;
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_get_my_entrypoint
|
||||
mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
|
||||
ldr x0, [x0]
|
||||
cbz x0, return
|
||||
b juno_do_reset_to_aarch32_state
|
||||
1:
|
||||
b 1b
|
||||
return:
|
||||
ret
|
||||
endfunc plat_get_my_entrypoint
|
||||
|
||||
/*
|
||||
* Emit a "movw r0, #imm16" which moves the lower
|
||||
* 16 bits of `_val` into r0.
|
||||
*/
|
||||
.macro emit_movw _reg_d, _val
|
||||
mov_imm \_reg_d, (0xe3000000 | \
|
||||
((\_val & 0xfff) | \
|
||||
((\_val & 0xf000) << 4)))
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Emit a "movt r0, #imm16" which moves the upper
|
||||
* 16 bits of `_val` into r0.
|
||||
*/
|
||||
.macro emit_movt _reg_d, _val
|
||||
mov_imm \_reg_d, (0xe3400000 | \
|
||||
(((\_val & 0x0fff0000) >> 16) | \
|
||||
((\_val & 0xf0000000) >> 12)))
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This function writes the trampoline code at HI-VEC (0xFFFF0000)
|
||||
* address which loads r0 with the entrypoint address for
|
||||
* BL32 (a.k.a SP_MIN) when EL3 is in AArch32 mode. A warm reset
|
||||
* to AArch32 mode is then requested by writing into RMR_EL3.
|
||||
*/
|
||||
func juno_reset_to_aarch32_state
|
||||
emit_movw w0, BL32_BASE
|
||||
emit_movt w1, BL32_BASE
|
||||
/* opcode "bx r0" to branch using r0 in AArch32 mode */
|
||||
mov_imm w2, 0xe12fff10
|
||||
|
||||
/* Write the above opcodes at HI-VECTOR location */
|
||||
mov_imm x3, HI_VECTOR_BASE
|
||||
str w0, [x3], #4
|
||||
str w1, [x3], #4
|
||||
str w2, [x3]
|
||||
|
||||
bl juno_do_reset_to_aarch32_state
|
||||
1:
|
||||
b 1b
|
||||
endfunc juno_reset_to_aarch32_state
|
||||
|
||||
#endif /* JUNO_AARCH32_EL3_RUNTIME */
|
||||
|
|
|
|||
|
|
@ -103,8 +103,8 @@
|
|||
#endif
|
||||
|
||||
#ifdef IMAGE_BL32
|
||||
# define PLAT_ARM_MMAP_ENTRIES 4
|
||||
# define MAX_XLAT_TABLES 3
|
||||
# define PLAT_ARM_MMAP_ENTRIES 5
|
||||
# define MAX_XLAT_TABLES 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -32,11 +32,15 @@
|
|||
#include <errno.h>
|
||||
#include <platform.h>
|
||||
#include <plat_arm.h>
|
||||
#include <sp805.h>
|
||||
#include <tbbr_img_def.h>
|
||||
#include <v2m_def.h>
|
||||
|
||||
#define RESET_REASON_WDOG_RESET (0x2)
|
||||
|
||||
void juno_reset_to_aarch32_state(void);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* The following function checks if Firmware update is needed,
|
||||
* by checking if TOC in FIP image is valid or watchdog reset happened.
|
||||
|
|
@ -85,3 +89,15 @@ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
|
|||
while (1)
|
||||
wfi();
|
||||
}
|
||||
|
||||
#if JUNO_AARCH32_EL3_RUNTIME
|
||||
void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
|
||||
{
|
||||
#if !ARM_DISABLE_TRUSTED_WDOG
|
||||
/* Disable watchdog before leaving BL1 */
|
||||
sp805_stop(ARM_SP805_TWDG_BASE);
|
||||
#endif
|
||||
|
||||
juno_reset_to_aarch32_state();
|
||||
}
|
||||
#endif /* JUNO_AARCH32_EL3_RUNTIME */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <bl_common.h>
|
||||
#include <desc_image_load.h>
|
||||
#include <plat_arm.h>
|
||||
|
||||
#if JUNO_AARCH32_EL3_RUNTIME
|
||||
/*******************************************************************************
|
||||
* This function changes the spsr for BL32 image to bypass
|
||||
* the check in BL1 AArch64 exception handler. This is needed in the aarch32
|
||||
* boot flow as the core comes up in aarch64 and to enter the BL32 image a warm
|
||||
* reset in aarch32 state is required.
|
||||
******************************************************************************/
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
int err = arm_bl2_handle_post_image_load(image_id);
|
||||
|
||||
if (!err && (image_id == BL32_IMAGE_ID)) {
|
||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
assert(bl_mem_params);
|
||||
bl_mem_params->ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
|
||||
DISABLE_ALL_EXCEPTIONS);
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
#endif /* JUNO_AARCH32_EL3_RUNTIME */
|
||||
|
|
@ -48,8 +48,14 @@ endif
|
|||
|
||||
PLAT_INCLUDES := -Iplat/arm/board/juno/include
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S
|
||||
PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S
|
||||
|
||||
# Flag to enable support for AArch32 state on JUNO
|
||||
JUNO_AARCH32_EL3_RUNTIME := 0
|
||||
$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
|
||||
$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
|
||||
|
||||
ifeq (${ARCH},aarch64)
|
||||
BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a57.S \
|
||||
lib/cpus/aarch64/cortex_a72.S \
|
||||
|
|
@ -59,6 +65,7 @@ BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
|||
${JUNO_SECURITY_SOURCES}
|
||||
|
||||
BL2_SOURCES += plat/arm/board/juno/juno_err.c \
|
||||
plat/arm/board/juno/juno_bl2_setup.c \
|
||||
${JUNO_SECURITY_SOURCES}
|
||||
|
||||
BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
|
||||
|
|
@ -71,6 +78,7 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
|||
${JUNO_GIC_SOURCES} \
|
||||
${JUNO_INTERCONNECT_SOURCES} \
|
||||
${JUNO_SECURITY_SOURCES}
|
||||
endif
|
||||
|
||||
# Enable workarounds for selected Cortex-A53 and A57 errata.
|
||||
ERRATA_A53_855873 := 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
#
|
||||
# Redistributions of source code must retain the above copyright notice, this
|
||||
# list of conditions and the following disclaimer.
|
||||
#
|
||||
# Redistributions in binary form must reproduce the above copyright notice,
|
||||
# this list of conditions and the following disclaimer in the documentation
|
||||
# and/or other materials provided with the distribution.
|
||||
#
|
||||
# Neither the name of ARM nor the names of its contributors may be used
|
||||
# to endorse or promote products derived from this software without specific
|
||||
# prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
# SP_MIN source files specific to JUNO platform
|
||||
BL32_SOURCES += lib/cpus/aarch32/cortex_a53.S \
|
||||
lib/cpus/aarch32/cortex_a57.S \
|
||||
lib/cpus/aarch32/cortex_a72.S \
|
||||
plat/arm/board/juno/juno_pm.c \
|
||||
plat/arm/board/juno/juno_topology.c \
|
||||
plat/arm/css/common/css_pm.c \
|
||||
plat/arm/css/common/css_topology.c \
|
||||
plat/arm/soc/common/soc_css_security.c \
|
||||
plat/arm/css/drivers/scp/css_pm_scpi.c \
|
||||
plat/arm/css/drivers/scpi/css_mhu.c \
|
||||
plat/arm/css/drivers/scpi/css_scpi.c \
|
||||
${JUNO_GIC_SOURCES} \
|
||||
${JUNO_INTERCONNECT_SOURCES} \
|
||||
${JUNO_SECURITY_SOURCES}
|
||||
|
||||
include plat/arm/common/sp_min/arm_sp_min.mk
|
||||
|
|
@ -44,6 +44,7 @@
|
|||
#pragma weak bl1_plat_arch_setup
|
||||
#pragma weak bl1_platform_setup
|
||||
#pragma weak bl1_plat_sec_mem_layout
|
||||
#pragma weak bl1_plat_prepare_exit
|
||||
|
||||
|
||||
/* Data structure which holds the extents of the trusted SRAM for BL1*/
|
||||
|
|
|
|||
|
|
@ -249,11 +249,7 @@ void bl2_plat_arch_setup(void)
|
|||
}
|
||||
|
||||
#if LOAD_IMAGE_V2
|
||||
/*******************************************************************************
|
||||
* This function can be used by the platforms to update/use image
|
||||
* information for given `image_id`.
|
||||
******************************************************************************/
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
int arm_bl2_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
int err = 0;
|
||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
|
|
@ -286,6 +282,15 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
|
|||
return err;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function can be used by the platforms to update/use image
|
||||
* information for given `image_id`.
|
||||
******************************************************************************/
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
return arm_bl2_handle_post_image_load(image_id);
|
||||
}
|
||||
|
||||
#else /* LOAD_IMAGE_V2 */
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -148,8 +148,14 @@ BL2_SOURCES += drivers/io/io_fip.c \
|
|||
plat/arm/common/arm_bl2_setup.c \
|
||||
plat/arm/common/arm_io_storage.c
|
||||
ifeq (${LOAD_IMAGE_V2},1)
|
||||
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c\
|
||||
plat/arm/common/arm_image_load.c \
|
||||
# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
|
||||
# the AArch32 descriptors.
|
||||
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
|
||||
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
|
||||
else
|
||||
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
|
||||
endif
|
||||
BL2_SOURCES += plat/arm/common/arm_image_load.c \
|
||||
common/desc_image_load.c
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <cpu_macros.S>
|
||||
#include <css_def.h>
|
||||
|
||||
.weak plat_secondary_cold_boot_setup
|
||||
.weak plat_get_my_entrypoint
|
||||
.globl css_calc_core_pos_swap_cluster
|
||||
.weak plat_is_my_cpu_primary
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* void plat_secondary_cold_boot_setup(void);
|
||||
* In the normal boot flow, cold-booting secondary
|
||||
* CPUs is not yet implemented and they panic.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_secondary_cold_boot_setup
|
||||
/* TODO: Implement secondary CPU cold boot setup on CSS platforms */
|
||||
cb_panic:
|
||||
b cb_panic
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* uintptr_t plat_get_my_entrypoint (void);
|
||||
*
|
||||
* Main job of this routine is to distinguish between a cold and a warm
|
||||
* boot. On CSS platforms, this distinction is based on the contents of
|
||||
* the Trusted Mailbox. It is initialised to zero by the SCP before the
|
||||
* AP cores are released from reset. Therefore, a zero mailbox means
|
||||
* it's a cold reset.
|
||||
*
|
||||
* This functions returns the contents of the mailbox, i.e.:
|
||||
* - 0 for a cold boot;
|
||||
* - the warm boot entrypoint for a warm boot.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func plat_get_my_entrypoint
|
||||
ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
|
||||
ldr r0, [r0]
|
||||
bx lr
|
||||
endfunc plat_get_my_entrypoint
|
||||
|
||||
/* -----------------------------------------------------------
|
||||
* unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr)
|
||||
* Utility function to calculate the core position by
|
||||
* swapping the cluster order. This is necessary in order to
|
||||
* match the format of the boot information passed by the SCP
|
||||
* and read in plat_is_my_cpu_primary below.
|
||||
* -----------------------------------------------------------
|
||||
*/
|
||||
func css_calc_core_pos_swap_cluster
|
||||
and r1, r0, #MPIDR_CPU_MASK
|
||||
and r0, r0, #MPIDR_CLUSTER_MASK
|
||||
eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
|
||||
add r0, r1, r0, LSR #6
|
||||
bx lr
|
||||
endfunc css_calc_core_pos_swap_cluster
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* unsigned int plat_is_my_cpu_primary (void);
|
||||
*
|
||||
* Find out whether the current cpu is the primary
|
||||
* cpu (applicable ony after a cold boot)
|
||||
* -----------------------------------------------------
|
||||
*/
|
||||
func plat_is_my_cpu_primary
|
||||
mov r10, lr
|
||||
bl plat_my_core_pos
|
||||
ldr r1, =SCP_BOOT_CFG_ADDR
|
||||
ldr r1, [r1]
|
||||
ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
|
||||
#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
|
||||
cmp r0, r1
|
||||
moveq r0, #1
|
||||
movne r0, #0
|
||||
bx r10
|
||||
endfunc plat_is_my_cpu_primary
|
||||
|
|
@ -36,7 +36,7 @@ PLAT_INCLUDES += -Iinclude/plat/arm/css/common \
|
|||
-Iinclude/plat/arm/css/common/aarch64
|
||||
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S
|
||||
PLAT_BL_COMMON_SOURCES += plat/arm/css/common/${ARCH}/css_helpers.S
|
||||
|
||||
BL1_SOURCES += plat/arm/css/common/css_bl1_setup.c
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include <assert.h>
|
||||
#include <css_pm.h>
|
||||
#include <debug.h>
|
||||
#include <plat_arm.h>
|
||||
#include "../scpi/css_scpi.h"
|
||||
#include "css_scp.h"
|
||||
|
||||
|
|
@ -134,6 +135,12 @@ void __dead2 css_scp_sys_shutdown(void)
|
|||
{
|
||||
uint32_t response;
|
||||
|
||||
/*
|
||||
* Disable GIC CPU interface to prevent pending interrupt
|
||||
* from waking up the AP from WFI.
|
||||
*/
|
||||
plat_arm_gic_cpuif_disable();
|
||||
|
||||
/* Send the power down request to the SCP */
|
||||
response = scpi_sys_power_state(scpi_system_shutdown);
|
||||
|
||||
|
|
@ -153,6 +160,12 @@ void __dead2 css_scp_sys_reboot(void)
|
|||
{
|
||||
uint32_t response;
|
||||
|
||||
/*
|
||||
* Disable GIC CPU interface to prevent pending interrupt
|
||||
* from waking up the AP from WFI.
|
||||
*/
|
||||
plat_arm_gic_cpuif_disable();
|
||||
|
||||
/* Send the system reset request to the SCP */
|
||||
response = scpi_sys_power_state(scpi_system_reboot);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue