rcar_gen3: drivers: pfc: V3M: Checkpatch cleanup
Checkpatch cleanups of the PFC init code and remaining SoC specific macros. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I3a9527db01afa909f61efd9556cc291e254a5e33
This commit is contained in:
Marek Vasut
parent
5b0dccd139
commit
4891ca8b17
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@ -13,434 +13,434 @@
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#include "../pfc_regs.h"
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/* Pin functon bit */
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#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
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#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
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#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
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#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U)
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#define GPSR0_DU_DB7 ((uint32_t)1U << 17U)
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#define GPSR0_DU_DB6 ((uint32_t)1U << 16U)
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#define GPSR0_DU_DB5 ((uint32_t)1U << 15U)
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#define GPSR0_DU_DB4 ((uint32_t)1U << 14U)
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#define GPSR0_DU_DB3 ((uint32_t)1U << 13U)
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#define GPSR0_DU_DB2 ((uint32_t)1U << 12U)
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#define GPSR0_DU_DG7 ((uint32_t)1U << 11U)
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#define GPSR0_DU_DG6 ((uint32_t)1U << 10U)
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#define GPSR0_DU_DG5 ((uint32_t)1U << 9U)
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#define GPSR0_DU_DG4 ((uint32_t)1U << 8U)
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#define GPSR0_DU_DG3 ((uint32_t)1U << 7U)
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#define GPSR0_DU_DG2 ((uint32_t)1U << 6U)
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#define GPSR0_DU_DR7 ((uint32_t)1U << 5U)
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#define GPSR0_DU_DR6 ((uint32_t)1U << 4U)
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#define GPSR0_DU_DR5 ((uint32_t)1U << 3U)
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#define GPSR0_DU_DR4 ((uint32_t)1U << 2U)
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#define GPSR0_DU_DR3 ((uint32_t)1U << 1U)
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#define GPSR0_DU_DR2 ((uint32_t)1U << 0U)
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#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
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#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
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#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
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#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U)
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#define GPSR0_DU_DB7 ((uint32_t)1U << 17U)
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#define GPSR0_DU_DB6 ((uint32_t)1U << 16U)
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#define GPSR0_DU_DB5 ((uint32_t)1U << 15U)
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#define GPSR0_DU_DB4 ((uint32_t)1U << 14U)
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#define GPSR0_DU_DB3 ((uint32_t)1U << 13U)
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#define GPSR0_DU_DB2 ((uint32_t)1U << 12U)
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#define GPSR0_DU_DG7 ((uint32_t)1U << 11U)
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#define GPSR0_DU_DG6 ((uint32_t)1U << 10U)
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#define GPSR0_DU_DG5 ((uint32_t)1U << 9U)
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#define GPSR0_DU_DG4 ((uint32_t)1U << 8U)
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#define GPSR0_DU_DG3 ((uint32_t)1U << 7U)
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#define GPSR0_DU_DG2 ((uint32_t)1U << 6U)
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#define GPSR0_DU_DR7 ((uint32_t)1U << 5U)
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#define GPSR0_DU_DR6 ((uint32_t)1U << 4U)
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#define GPSR0_DU_DR5 ((uint32_t)1U << 3U)
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#define GPSR0_DU_DR4 ((uint32_t)1U << 2U)
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#define GPSR0_DU_DR3 ((uint32_t)1U << 1U)
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#define GPSR0_DU_DR2 ((uint32_t)1U << 0U)
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#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U)
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#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U)
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#define GPSR1_CANFD_CLK ((uint32_t)1U << 25U)
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#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U)
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#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U)
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#define GPSR1_CANFD0_RX ((uint32_t)1U << 22U)
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#define GPSR1_CANFD0_TX ((uint32_t)1U << 21U)
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#define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U)
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#define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U)
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#define GPSR1_AVB0_LINK ((uint32_t)1U << 18U)
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#define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U)
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#define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U)
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#define GPSR1_AVB0_MDC ((uint32_t)1U << 15U)
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#define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U)
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#define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U)
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#define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U)
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#define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U)
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#define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U)
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#define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U)
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#define GPSR1_AVB0_TXC ((uint32_t)1U << 8U)
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#define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U)
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#define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U)
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#define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U)
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#define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U)
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#define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U)
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#define GPSR1_AVB0_RXC ((uint32_t)1U << 2U)
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#define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U)
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#define GPSR1_IRQ0 ((uint32_t)1U << 0U)
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#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U)
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#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U)
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#define GPSR1_CANFD_CLK ((uint32_t)1U << 25U)
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#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U)
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#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U)
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#define GPSR1_CANFD0_RX ((uint32_t)1U << 22U)
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#define GPSR1_CANFD0_TX ((uint32_t)1U << 21U)
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#define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U)
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#define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U)
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#define GPSR1_AVB0_LINK ((uint32_t)1U << 18U)
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#define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U)
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#define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U)
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#define GPSR1_AVB0_MDC ((uint32_t)1U << 15U)
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#define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U)
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#define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U)
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#define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U)
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#define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U)
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#define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U)
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#define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U)
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#define GPSR1_AVB0_TXC ((uint32_t)1U << 8U)
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#define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U)
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#define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U)
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#define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U)
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#define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U)
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#define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U)
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#define GPSR1_AVB0_RXC ((uint32_t)1U << 2U)
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#define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U)
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#define GPSR1_IRQ0 ((uint32_t)1U << 0U)
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#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U)
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#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U)
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#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U)
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#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U)
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#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U)
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#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U)
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#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U)
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#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U)
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#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U)
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#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U)
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#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U)
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#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U)
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#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U)
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#define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U)
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#define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U)
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#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U)
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#define GPSR2_VI0_CLK ((uint32_t)1U << 0U)
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#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U)
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#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U)
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#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U)
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#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U)
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#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U)
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#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U)
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#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U)
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#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U)
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#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U)
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#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U)
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#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U)
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#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U)
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#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U)
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#define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U)
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#define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U)
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#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U)
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#define GPSR2_VI0_CLK ((uint32_t)1U << 0U)
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#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U)
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#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U)
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#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U)
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#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U)
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#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U)
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#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U)
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#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U)
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#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U)
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#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U)
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#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U)
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#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U)
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#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U)
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#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U)
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#define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U)
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#define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U)
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#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U)
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#define GPSR3_VI1_CLK ((uint32_t)1U << 0U)
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#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U)
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#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U)
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#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U)
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#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U)
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#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U)
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#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U)
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#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U)
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#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U)
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#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U)
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#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U)
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#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U)
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#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U)
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#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U)
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#define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U)
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#define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U)
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#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U)
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#define GPSR3_VI1_CLK ((uint32_t)1U << 0U)
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#define GPSR4_SDA2 ((uint32_t)1U << 5U)
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#define GPSR4_SCL2 ((uint32_t)1U << 4U)
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#define GPSR4_SDA1 ((uint32_t)1U << 3U)
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#define GPSR4_SCL1 ((uint32_t)1U << 2U)
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#define GPSR4_SDA0 ((uint32_t)1U << 1U)
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#define GPSR4_SCL0 ((uint32_t)1U << 0U)
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#define GPSR4_SDA2 ((uint32_t)1U << 5U)
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#define GPSR4_SCL2 ((uint32_t)1U << 4U)
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#define GPSR4_SDA1 ((uint32_t)1U << 3U)
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#define GPSR4_SCL1 ((uint32_t)1U << 2U)
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#define GPSR4_SDA0 ((uint32_t)1U << 1U)
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#define GPSR4_SCL0 ((uint32_t)1U << 0U)
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#define GPSR5_RPC_INT_N ((uint32_t)1U << 14U)
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#define GPSR5_RPC_WP_N ((uint32_t)1U << 13U)
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#define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U)
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#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U)
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#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U)
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#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U)
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#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
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#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
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#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U)
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#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U)
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#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U)
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#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U)
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#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
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#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
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#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U)
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#define GPSR5_RPC_INT_N ((uint32_t)1U << 14U)
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#define GPSR5_RPC_WP_N ((uint32_t)1U << 13U)
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#define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U)
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#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U)
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#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U)
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#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U)
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#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
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#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
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#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U)
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#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U)
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#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U)
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#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U)
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#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
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#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
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#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U)
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#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
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#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
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#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
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#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
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#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
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#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
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#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
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#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
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#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
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#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
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#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
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#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
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#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
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#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
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#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
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#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
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#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U)
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#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U)
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#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U)
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#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U)
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#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U)
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#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U)
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#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U)
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#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U)
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#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U)
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#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U)
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#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
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#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
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#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
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#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U)
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#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U)
|
||||
#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U)
|
||||
#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U)
|
||||
#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U)
|
||||
#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U)
|
||||
#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U)
|
||||
#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U)
|
||||
#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U)
|
||||
#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U)
|
||||
#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U)
|
||||
#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U)
|
||||
|
||||
#define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U)
|
||||
#define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U)
|
||||
#define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U)
|
||||
#define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U)
|
||||
#define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U)
|
||||
#define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U)
|
||||
#define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U)
|
||||
#define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U)
|
||||
#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U)
|
||||
#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U)
|
||||
#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U)
|
||||
#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U)
|
||||
#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U)
|
||||
#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U)
|
||||
#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U)
|
||||
#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U)
|
||||
#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U)
|
||||
#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U)
|
||||
#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U)
|
||||
#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U)
|
||||
#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U)
|
||||
#define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U)
|
||||
#define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U)
|
||||
#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U)
|
||||
#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U)
|
||||
#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U)
|
||||
#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U)
|
||||
#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U)
|
||||
#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U)
|
||||
#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U)
|
||||
#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U)
|
||||
#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U)
|
||||
#define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U)
|
||||
#define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U)
|
||||
#define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U)
|
||||
#define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U)
|
||||
#define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U)
|
||||
#define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U)
|
||||
#define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U)
|
||||
#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U)
|
||||
#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U)
|
||||
#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U)
|
||||
#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U)
|
||||
#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U)
|
||||
#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U)
|
||||
#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U)
|
||||
#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U)
|
||||
#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U)
|
||||
#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U)
|
||||
#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U)
|
||||
#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U)
|
||||
#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U)
|
||||
#define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U)
|
||||
#define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U)
|
||||
#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U)
|
||||
#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U)
|
||||
#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U)
|
||||
#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U)
|
||||
#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U)
|
||||
#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U)
|
||||
#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U)
|
||||
#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U)
|
||||
#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U)
|
||||
#define PUEN0_PUEN_TDI ((uint32_t)1U << 30U)
|
||||
#define PUEN0_PUEN_TMS ((uint32_t)1U << 29U)
|
||||
#define PUEN0_PUEN_TCK ((uint32_t)1U << 28U)
|
||||
#define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U)
|
||||
#define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U)
|
||||
#define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U)
|
||||
#define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U)
|
||||
#define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U)
|
||||
#define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U)
|
||||
#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U)
|
||||
#define PUEN0_PUEN_TDI ((uint32_t)1U << 30U)
|
||||
#define PUEN0_PUEN_TMS ((uint32_t)1U << 29U)
|
||||
#define PUEN0_PUEN_TCK ((uint32_t)1U << 28U)
|
||||
#define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U)
|
||||
#define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U)
|
||||
#define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U)
|
||||
#define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U)
|
||||
#define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U)
|
||||
#define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U)
|
||||
#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U)
|
||||
#define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U)
|
||||
#define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U)
|
||||
#define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U)
|
||||
#define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U)
|
||||
#define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U)
|
||||
#define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U)
|
||||
#define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U)
|
||||
#define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U)
|
||||
#define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U)
|
||||
#define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U)
|
||||
#define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U)
|
||||
#define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U)
|
||||
#define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U)
|
||||
#define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U)
|
||||
#define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U)
|
||||
#define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U)
|
||||
#define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U)
|
||||
#define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U)
|
||||
#define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U)
|
||||
#define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U)
|
||||
#define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U)
|
||||
#define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U)
|
||||
#define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U)
|
||||
#define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U)
|
||||
#define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U)
|
||||
#define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U)
|
||||
#define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U)
|
||||
#define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U)
|
||||
#define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U)
|
||||
#define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U)
|
||||
#define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U)
|
||||
#define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U)
|
||||
#define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U)
|
||||
#define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U)
|
||||
#define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U)
|
||||
#define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U)
|
||||
#define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U)
|
||||
#define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U)
|
||||
#define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U)
|
||||
#define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U)
|
||||
#define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U)
|
||||
#define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U)
|
||||
#define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U)
|
||||
#define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U)
|
||||
#define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U)
|
||||
#define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U)
|
||||
#define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U)
|
||||
#define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U)
|
||||
#define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U)
|
||||
#define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U)
|
||||
#define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U)
|
||||
#define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U)
|
||||
#define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U)
|
||||
#define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U)
|
||||
#define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U)
|
||||
#define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U)
|
||||
#define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U)
|
||||
#define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U)
|
||||
#define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U)
|
||||
#define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U)
|
||||
#define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U)
|
||||
#define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U)
|
||||
#define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U)
|
||||
#define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U)
|
||||
#define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U)
|
||||
#define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U)
|
||||
#define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U)
|
||||
#define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U)
|
||||
#define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U)
|
||||
#define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U)
|
||||
#define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U)
|
||||
#define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U)
|
||||
#define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U)
|
||||
#define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U)
|
||||
#define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U)
|
||||
#define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U)
|
||||
#define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U)
|
||||
#define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U)
|
||||
#define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U)
|
||||
#define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U)
|
||||
#define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U)
|
||||
#define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U)
|
||||
#define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U)
|
||||
#define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U)
|
||||
#define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U)
|
||||
#define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U)
|
||||
#define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U)
|
||||
#define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U)
|
||||
#define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U)
|
||||
#define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U)
|
||||
#define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U)
|
||||
#define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U)
|
||||
#define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U)
|
||||
#define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U)
|
||||
#define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U)
|
||||
#define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U)
|
||||
#define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U)
|
||||
#define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U)
|
||||
#define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U)
|
||||
#define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U)
|
||||
#define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U)
|
||||
#define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U)
|
||||
#define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U)
|
||||
#define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U)
|
||||
#define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U)
|
||||
#define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U)
|
||||
#define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U)
|
||||
#define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U)
|
||||
#define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U)
|
||||
#define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U)
|
||||
#define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U)
|
||||
#define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U)
|
||||
#define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U)
|
||||
#define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U)
|
||||
#define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U)
|
||||
#define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U)
|
||||
#define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U)
|
||||
#define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U)
|
||||
#define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U)
|
||||
#define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U)
|
||||
#define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U)
|
||||
#define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U)
|
||||
#define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U)
|
||||
#define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
#define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U)
|
||||
#define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U)
|
||||
#define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U)
|
||||
#define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U)
|
||||
#define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U)
|
||||
#define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U)
|
||||
#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U)
|
||||
#define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U)
|
||||
#define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U)
|
||||
#define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U)
|
||||
#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U)
|
||||
#define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U)
|
||||
#define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U)
|
||||
#define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U)
|
||||
#define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U)
|
||||
#define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U)
|
||||
#define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U)
|
||||
#define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U)
|
||||
#define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U)
|
||||
#define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U)
|
||||
#define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U)
|
||||
#define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U)
|
||||
#define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U)
|
||||
#define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U)
|
||||
#define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U)
|
||||
#define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U)
|
||||
#define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U)
|
||||
#define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U)
|
||||
#define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U)
|
||||
#define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U)
|
||||
#define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U)
|
||||
#define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U)
|
||||
#define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U)
|
||||
#define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U)
|
||||
#define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U)
|
||||
#define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U)
|
||||
#define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U)
|
||||
#define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U)
|
||||
#define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U)
|
||||
#define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U)
|
||||
#define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U)
|
||||
#define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U)
|
||||
#define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U)
|
||||
#define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U)
|
||||
#define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U)
|
||||
#define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U)
|
||||
#define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U)
|
||||
#define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U)
|
||||
#define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U)
|
||||
#define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U)
|
||||
#define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U)
|
||||
#define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U)
|
||||
#define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U)
|
||||
#define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U)
|
||||
#define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U)
|
||||
#define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U)
|
||||
#define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U)
|
||||
#define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U)
|
||||
#define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U)
|
||||
#define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U)
|
||||
#define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U)
|
||||
#define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U)
|
||||
#define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U)
|
||||
#define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U)
|
||||
#define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U)
|
||||
#define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U)
|
||||
#define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U)
|
||||
#define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U)
|
||||
#define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U)
|
||||
#define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U)
|
||||
#define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U)
|
||||
#define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U)
|
||||
#define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U)
|
||||
#define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U)
|
||||
#define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U)
|
||||
#define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U)
|
||||
#define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U)
|
||||
#define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U)
|
||||
#define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U)
|
||||
#define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U)
|
||||
#define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U)
|
||||
#define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U)
|
||||
#define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U)
|
||||
#define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U)
|
||||
#define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U)
|
||||
#define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U)
|
||||
#define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U)
|
||||
#define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U)
|
||||
#define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U)
|
||||
#define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U)
|
||||
#define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U)
|
||||
#define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U)
|
||||
#define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U)
|
||||
#define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U)
|
||||
#define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U)
|
||||
#define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U)
|
||||
#define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U)
|
||||
#define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U)
|
||||
#define PUD2_PUD_SDA2 ((uint32_t)1U << 6U)
|
||||
#define PUD2_PUD_SCL2 ((uint32_t)1U << 5U)
|
||||
#define PUD2_PUD_SDA1 ((uint32_t)1U << 4U)
|
||||
#define PUD2_PUD_SCL1 ((uint32_t)1U << 3U)
|
||||
#define PUD2_PUD_SDA0 ((uint32_t)1U << 2U)
|
||||
#define PUD2_PUD_SCL0 ((uint32_t)1U << 1U)
|
||||
#define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U)
|
||||
#define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U)
|
||||
#define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U)
|
||||
#define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U)
|
||||
#define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U)
|
||||
#define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U)
|
||||
#define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U)
|
||||
#define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U)
|
||||
#define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U)
|
||||
#define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U)
|
||||
#define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U)
|
||||
#define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U)
|
||||
#define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U)
|
||||
#define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U)
|
||||
#define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U)
|
||||
#define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U)
|
||||
#define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U)
|
||||
#define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U)
|
||||
#define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U)
|
||||
#define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U)
|
||||
#define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U)
|
||||
#define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U)
|
||||
#define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U)
|
||||
#define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U)
|
||||
#define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U)
|
||||
#define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U)
|
||||
#define PUD2_PUD_SDA2 ((uint32_t)1U << 6U)
|
||||
#define PUD2_PUD_SCL2 ((uint32_t)1U << 5U)
|
||||
#define PUD2_PUD_SDA1 ((uint32_t)1U << 4U)
|
||||
#define PUD2_PUD_SCL1 ((uint32_t)1U << 3U)
|
||||
#define PUD2_PUD_SDA0 ((uint32_t)1U << 2U)
|
||||
#define PUD2_PUD_SCL0 ((uint32_t)1U << 1U)
|
||||
#define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U)
|
||||
|
||||
#define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U)
|
||||
#define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U)
|
||||
#define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
#define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U)
|
||||
#define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U)
|
||||
#define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
|
||||
#define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U)
|
||||
#define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U)
|
||||
#define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U)
|
||||
#define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U)
|
||||
#define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U)
|
||||
#define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U)
|
||||
#define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U)
|
||||
#define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U)
|
||||
#define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U)
|
||||
#define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U)
|
||||
#define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U)
|
||||
#define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U)
|
||||
#define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U)
|
||||
#define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U)
|
||||
#define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U)
|
||||
#define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U)
|
||||
#define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U)
|
||||
#define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U)
|
||||
#define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U)
|
||||
#define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U)
|
||||
#define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U)
|
||||
#define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U)
|
||||
|
||||
/* SCIF3 Registers for Dummy write */
|
||||
#define SCIF3_BASE (0xE6C50000U)
|
||||
|
|
@ -449,7 +449,7 @@
|
|||
#define SCFCR_DATA (0x0000U)
|
||||
|
||||
/* Realtime module stop control */
|
||||
#define CPG_BASE (0xE6150000U)
|
||||
#define CPG_BASE (0xE6150000U)
|
||||
#define CPG_MSTPSR0 (CPG_BASE + 0x0030U)
|
||||
#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U)
|
||||
#define RMSTPCR0_RTDMAC (0x00200000U)
|
||||
|
|
@ -495,7 +495,7 @@ static void StartRtDma0_Descriptor(void)
|
|||
uint32_t reg;
|
||||
|
||||
/* Module stop clear */
|
||||
while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
|
||||
while ((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
|
||||
reg = mmio_read_32(CPG_RMSTPCR0);
|
||||
reg &= ~RMSTPCR0_RTDMAC;
|
||||
cpg_write(CPG_RMSTPCR0, reg);
|
||||
|
|
@ -562,7 +562,6 @@ void pfc_init_v3m(void)
|
|||
| GPSR5_QSPI0_MOSI_IO0
|
||||
| GPSR5_QSPI0_SPCLK);
|
||||
|
||||
|
||||
/* initialize peripheral function select */
|
||||
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
|
||||
| IPSR_24_FUNC(0)
|
||||
|
|
@ -718,7 +717,7 @@ void pfc_init_v3m(void)
|
|||
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
|
||||
|
||||
/* initialize Pull enable */
|
||||
pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK
|
||||
pfc_reg_write(PFC_PUEN0, PUEN0_PUEN_VI0_CLK
|
||||
| PUEN0_PUEN_TDI
|
||||
| PUEN0_PUEN_TMS
|
||||
| PUEN0_PUEN_TCK
|
||||
|
|
@ -746,7 +745,7 @@ void pfc_init_v3m(void)
|
|||
| PUEN0_PUEN_DU_DR3
|
||||
| PUEN0_PUEN_DU_DR2);
|
||||
|
||||
pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11
|
||||
pfc_reg_write(PFC_PUEN1, PUEN1_PUEN_VI1_DATA11
|
||||
| PUEN1_PUEN_VI1_DATA10
|
||||
| PUEN1_PUEN_VI1_DATA9
|
||||
| PUEN1_PUEN_VI1_DATA8
|
||||
|
|
@ -774,7 +773,7 @@ void pfc_init_v3m(void)
|
|||
| PUEN1_PUEN_VI0_DATA2
|
||||
| PUEN1_PUEN_VI0_DATA1);
|
||||
|
||||
pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK
|
||||
pfc_reg_write(PFC_PUEN2, PUEN2_PUEN_CANFD_CLK
|
||||
| PUEN2_PUEN_CANFD1_RX
|
||||
| PUEN2_PUEN_CANFD1_TX
|
||||
| PUEN2_PUEN_CANFD0_RX
|
||||
|
|
@ -799,11 +798,11 @@ void pfc_init_v3m(void)
|
|||
| PUEN2_PUEN_AVB0_RX_CTL
|
||||
| PUEN2_PUEN_VI1_FIELD);
|
||||
|
||||
pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT
|
||||
pfc_reg_write(PFC_PUEN3, PUEN3_PUEN_DIGRF_CLKOUT
|
||||
| PUEN3_PUEN_DIGRF_CLKIN);
|
||||
|
||||
/* initialize PUD Control */
|
||||
pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK
|
||||
pfc_reg_write(PFC_PUD0, PUD0_PUD_VI0_CLK
|
||||
| PUD0_PUD_IRQ0
|
||||
| PUD0_PUD_FSCLKST_N
|
||||
| PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
|
||||
|
|
@ -829,7 +828,7 @@ void pfc_init_v3m(void)
|
|||
| PUD0_PUD_DU_DR3
|
||||
| PUD0_PUD_DU_DR2);
|
||||
|
||||
pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11
|
||||
pfc_reg_write(PFC_PUD1, PUD1_PUD_VI1_DATA11
|
||||
| PUD1_PUD_VI1_DATA10
|
||||
| PUD1_PUD_VI1_DATA9
|
||||
| PUD1_PUD_VI1_DATA8
|
||||
|
|
@ -861,7 +860,7 @@ void pfc_init_v3m(void)
|
|||
| PUD1_PUD_VI0_HSYNC_N
|
||||
| PUD1_PUD_VI0_CLKENB);
|
||||
|
||||
pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK
|
||||
pfc_reg_write(PFC_PUD2, PUD2_PUD_CANFD_CLK
|
||||
| PUD2_PUD_CANFD1_RX
|
||||
| PUD2_PUD_CANFD1_TX
|
||||
| PUD2_PUD_CANFD0_RX
|
||||
|
|
@ -869,11 +868,11 @@ void pfc_init_v3m(void)
|
|||
| PUD2_PUD_AVB0_AVTP_CAPTURE
|
||||
| PUD2_PUD_VI1_FIELD);
|
||||
|
||||
pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT
|
||||
pfc_reg_write(PFC_PUD3, PUD3_PUD_DIGRF_CLKOUT
|
||||
| PUD3_PUD_DIGRF_CLKIN);
|
||||
|
||||
/* initialize Module Select */
|
||||
pfc_reg_write(PFC_MOD_SEL0,0x00000000);
|
||||
pfc_reg_write(PFC_MOD_SEL0, 0x00000000);
|
||||
|
||||
// gpio
|
||||
/* initialize positive/negative logic select */
|
||||
|
|
|
|||
Loading…
Reference in New Issue