rcar_gen3: drivers: pfc: V3M: Checkpatch cleanup
Checkpatch cleanups of the PFC init code and remaining SoC specific macros. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I3a9527db01afa909f61efd9556cc291e254a5e33
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@ -495,7 +495,7 @@ static void StartRtDma0_Descriptor(void)
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uint32_t reg;
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uint32_t reg;
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/* Module stop clear */
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/* Module stop clear */
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while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
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while ((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
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reg = mmio_read_32(CPG_RMSTPCR0);
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reg = mmio_read_32(CPG_RMSTPCR0);
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reg &= ~RMSTPCR0_RTDMAC;
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reg &= ~RMSTPCR0_RTDMAC;
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cpg_write(CPG_RMSTPCR0, reg);
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cpg_write(CPG_RMSTPCR0, reg);
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@ -562,7 +562,6 @@ void pfc_init_v3m(void)
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| GPSR5_QSPI0_MOSI_IO0
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| GPSR5_QSPI0_MOSI_IO0
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| GPSR5_QSPI0_SPCLK);
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| GPSR5_QSPI0_SPCLK);
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/* initialize peripheral function select */
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/* initialize peripheral function select */
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pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
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pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
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| IPSR_24_FUNC(0)
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| IPSR_24_FUNC(0)
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@ -718,7 +717,7 @@ void pfc_init_v3m(void)
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pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
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pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
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/* initialize Pull enable */
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/* initialize Pull enable */
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pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK
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pfc_reg_write(PFC_PUEN0, PUEN0_PUEN_VI0_CLK
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| PUEN0_PUEN_TDI
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| PUEN0_PUEN_TDI
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| PUEN0_PUEN_TMS
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| PUEN0_PUEN_TMS
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| PUEN0_PUEN_TCK
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| PUEN0_PUEN_TCK
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@ -746,7 +745,7 @@ void pfc_init_v3m(void)
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| PUEN0_PUEN_DU_DR3
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| PUEN0_PUEN_DU_DR3
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| PUEN0_PUEN_DU_DR2);
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| PUEN0_PUEN_DU_DR2);
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pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11
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pfc_reg_write(PFC_PUEN1, PUEN1_PUEN_VI1_DATA11
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| PUEN1_PUEN_VI1_DATA10
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| PUEN1_PUEN_VI1_DATA10
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| PUEN1_PUEN_VI1_DATA9
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| PUEN1_PUEN_VI1_DATA9
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| PUEN1_PUEN_VI1_DATA8
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| PUEN1_PUEN_VI1_DATA8
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@ -774,7 +773,7 @@ void pfc_init_v3m(void)
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| PUEN1_PUEN_VI0_DATA2
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| PUEN1_PUEN_VI0_DATA2
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| PUEN1_PUEN_VI0_DATA1);
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| PUEN1_PUEN_VI0_DATA1);
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pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK
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pfc_reg_write(PFC_PUEN2, PUEN2_PUEN_CANFD_CLK
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| PUEN2_PUEN_CANFD1_RX
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| PUEN2_PUEN_CANFD1_RX
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| PUEN2_PUEN_CANFD1_TX
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| PUEN2_PUEN_CANFD1_TX
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| PUEN2_PUEN_CANFD0_RX
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| PUEN2_PUEN_CANFD0_RX
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@ -799,11 +798,11 @@ void pfc_init_v3m(void)
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| PUEN2_PUEN_AVB0_RX_CTL
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| PUEN2_PUEN_AVB0_RX_CTL
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| PUEN2_PUEN_VI1_FIELD);
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| PUEN2_PUEN_VI1_FIELD);
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pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT
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pfc_reg_write(PFC_PUEN3, PUEN3_PUEN_DIGRF_CLKOUT
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| PUEN3_PUEN_DIGRF_CLKIN);
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| PUEN3_PUEN_DIGRF_CLKIN);
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/* initialize PUD Control */
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/* initialize PUD Control */
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pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK
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pfc_reg_write(PFC_PUD0, PUD0_PUD_VI0_CLK
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| PUD0_PUD_IRQ0
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| PUD0_PUD_IRQ0
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| PUD0_PUD_FSCLKST_N
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| PUD0_PUD_FSCLKST_N
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| PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
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| PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
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@ -829,7 +828,7 @@ void pfc_init_v3m(void)
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| PUD0_PUD_DU_DR3
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| PUD0_PUD_DU_DR3
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| PUD0_PUD_DU_DR2);
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| PUD0_PUD_DU_DR2);
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pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11
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pfc_reg_write(PFC_PUD1, PUD1_PUD_VI1_DATA11
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| PUD1_PUD_VI1_DATA10
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| PUD1_PUD_VI1_DATA10
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| PUD1_PUD_VI1_DATA9
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| PUD1_PUD_VI1_DATA9
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| PUD1_PUD_VI1_DATA8
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| PUD1_PUD_VI1_DATA8
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@ -861,7 +860,7 @@ void pfc_init_v3m(void)
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| PUD1_PUD_VI0_HSYNC_N
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| PUD1_PUD_VI0_HSYNC_N
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| PUD1_PUD_VI0_CLKENB);
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| PUD1_PUD_VI0_CLKENB);
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pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK
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pfc_reg_write(PFC_PUD2, PUD2_PUD_CANFD_CLK
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| PUD2_PUD_CANFD1_RX
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| PUD2_PUD_CANFD1_RX
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| PUD2_PUD_CANFD1_TX
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| PUD2_PUD_CANFD1_TX
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| PUD2_PUD_CANFD0_RX
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| PUD2_PUD_CANFD0_RX
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@ -869,11 +868,11 @@ void pfc_init_v3m(void)
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| PUD2_PUD_AVB0_AVTP_CAPTURE
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| PUD2_PUD_AVB0_AVTP_CAPTURE
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| PUD2_PUD_VI1_FIELD);
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| PUD2_PUD_VI1_FIELD);
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pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT
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pfc_reg_write(PFC_PUD3, PUD3_PUD_DIGRF_CLKOUT
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| PUD3_PUD_DIGRF_CLKIN);
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| PUD3_PUD_DIGRF_CLKIN);
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/* initialize Module Select */
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/* initialize Module Select */
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pfc_reg_write(PFC_MOD_SEL0,0x00000000);
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pfc_reg_write(PFC_MOD_SEL0, 0x00000000);
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// gpio
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// gpio
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/* initialize positive/negative logic select */
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/* initialize positive/negative logic select */
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