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rcar_gen3: drivers: pfc: V3M: Checkpatch cleanup 

Checkpatch cleanups of the PFC init code and remaining SoC specific macros.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I3a9527db01afa909f61efd9556cc291e254a5e33
This commit is contained in:
Marek Vasut 2019-06-17 19:15:33 +02:00
parent 5b0dccd139
commit 4891ca8b17
1 changed files with 422 additions and 423 deletions
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21
drivers/staging/renesas/rcar/pfc/V3M/pfc_init_v3m.c
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@ -495,7 +495,7 @@ static void StartRtDma0_Descriptor(void)
uint32_t reg;
/* Module stop clear */
while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
while ((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) {
reg = mmio_read_32(CPG_RMSTPCR0);
reg &= ~RMSTPCR0_RTDMAC;
cpg_write(CPG_RMSTPCR0, reg);
@ -562,7 +562,6 @@ void pfc_init_v3m(void)
| GPSR5_QSPI0_MOSI_IO0
| GPSR5_QSPI0_SPCLK);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
@ -718,7 +717,7 @@ void pfc_init_v3m(void)
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);
/* initialize Pull enable */
pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK
pfc_reg_write(PFC_PUEN0, PUEN0_PUEN_VI0_CLK
| PUEN0_PUEN_TDI
| PUEN0_PUEN_TMS
| PUEN0_PUEN_TCK
@ -746,7 +745,7 @@ void pfc_init_v3m(void)
| PUEN0_PUEN_DU_DR3
| PUEN0_PUEN_DU_DR2);
pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11
pfc_reg_write(PFC_PUEN1, PUEN1_PUEN_VI1_DATA11
| PUEN1_PUEN_VI1_DATA10
| PUEN1_PUEN_VI1_DATA9
| PUEN1_PUEN_VI1_DATA8
@ -774,7 +773,7 @@ void pfc_init_v3m(void)
| PUEN1_PUEN_VI0_DATA2
| PUEN1_PUEN_VI0_DATA1);
pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK
pfc_reg_write(PFC_PUEN2, PUEN2_PUEN_CANFD_CLK
| PUEN2_PUEN_CANFD1_RX
| PUEN2_PUEN_CANFD1_TX
| PUEN2_PUEN_CANFD0_RX
@ -799,11 +798,11 @@ void pfc_init_v3m(void)
| PUEN2_PUEN_AVB0_RX_CTL
| PUEN2_PUEN_VI1_FIELD);
pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT
pfc_reg_write(PFC_PUEN3, PUEN3_PUEN_DIGRF_CLKOUT
| PUEN3_PUEN_DIGRF_CLKIN);
/* initialize PUD Control */
pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK
pfc_reg_write(PFC_PUD0, PUD0_PUD_VI0_CLK
| PUD0_PUD_IRQ0
| PUD0_PUD_FSCLKST_N
| PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE
@ -829,7 +828,7 @@ void pfc_init_v3m(void)
| PUD0_PUD_DU_DR3
| PUD0_PUD_DU_DR2);
pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11
pfc_reg_write(PFC_PUD1, PUD1_PUD_VI1_DATA11
| PUD1_PUD_VI1_DATA10
| PUD1_PUD_VI1_DATA9
| PUD1_PUD_VI1_DATA8
@ -861,7 +860,7 @@ void pfc_init_v3m(void)
| PUD1_PUD_VI0_HSYNC_N
| PUD1_PUD_VI0_CLKENB);
pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK
pfc_reg_write(PFC_PUD2, PUD2_PUD_CANFD_CLK
| PUD2_PUD_CANFD1_RX
| PUD2_PUD_CANFD1_TX
| PUD2_PUD_CANFD0_RX
@ -869,11 +868,11 @@ void pfc_init_v3m(void)
| PUD2_PUD_AVB0_AVTP_CAPTURE
| PUD2_PUD_VI1_FIELD);
pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT
pfc_reg_write(PFC_PUD3, PUD3_PUD_DIGRF_CLKOUT
| PUD3_PUD_DIGRF_CLKIN);
/* initialize Module Select */
pfc_reg_write(PFC_MOD_SEL0,0x00000000);
pfc_reg_write(PFC_MOD_SEL0, 0x00000000);
// gpio
/* initialize positive/negative logic select */