Reset debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR
In order to avoid unexpected traps into EL3/MON mode, this patch resets the debug registers, MDCR_EL3 and MDCR_EL2 for AArch64, and SDCR and HDCR for AArch32. MDCR_EL3/SDCR is zero'ed when EL3/MON mode is entered, at the start of BL1 and BL31/SMP_MIN. For MDCR_EL2/HDCR, this patch zero's the bits that are architecturally UNKNOWN values on reset. This is done when exiting from EL3/MON mode but only on platforms that support EL2/HYP mode but choose to exit to EL1/SVC mode. Fixes ARM-software/tf-issues#430 Change-Id: Idb992232163c072faa08892251b5626ae4c3a5b6 Signed-off-by: David Cunado <david.cunado@arm.com>
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@ -67,6 +67,14 @@
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orr r0, r0, #SCR_SIF_BIT
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stcopr r0, SCR
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/* -----------------------------------------------------------------
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* Reset those registers that may have architecturally unknown reset
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* values
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* -----------------------------------------------------------------
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*/
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mov r0, #0
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stcopr r0, SDCR
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/* -----------------------------------------------------
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* Enable the Asynchronous data abort now that the
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* exception vectors have been setup.
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@ -77,6 +77,13 @@
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*/
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mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT)
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msr scr_el3, x0
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/* ---------------------------------------------------------------------
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* Reset registers that may have architecturally unknown reset values
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* ---------------------------------------------------------------------
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*/
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msr mdcr_el3, xzr
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/* ---------------------------------------------------------------------
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* Enable External Aborts and SError Interrupts now that the exception
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* vectors have been setup.
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@ -318,6 +318,11 @@
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#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
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/* PMCR definitions */
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#define PMCR_N_SHIFT 11
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#define PMCR_N_MASK 0x1f
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#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
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/*******************************************************************************
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the
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* system level implementation of the Generic Timer.
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@ -375,6 +380,11 @@
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#define CSSELR p15, 2, c0, c0, 0
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#define CCSIDR p15, 1, c0, c0, 0
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/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define HDCR p15, 4, c1, c1, 1
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#define SDCR p15, 0, c1, c3, 1
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#define PMCR p15, 0, c9, c12, 0
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/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define ICC_IAR1 p15, 0, c12, c12, 0
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#define ICC_IAR0 p15, 0, c12, c8, 0
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@ -249,6 +249,9 @@ DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
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DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
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DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
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/*
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* TLBI operation prototypes
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*/
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@ -411,4 +411,9 @@
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#define CNTACR_RWVT_SHIFT 0x4
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#define CNTACR_RWPT_SHIFT 0x5
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/* PMCR_EL0 definitions */
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#define PMCR_EL0_N_SHIFT 11
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#define PMCR_EL0_N_MASK 0x1f
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#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
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#endif /* __ARCH_H__ */
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@ -279,6 +279,9 @@ DEFINE_SYSREG_READ_FUNC(isr_el1)
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DEFINE_SYSREG_READ_FUNC(ctr_el0)
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DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
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DEFINE_SYSREG_READ_FUNC(pmcr_el0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
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@ -200,7 +200,10 @@ void cm_prepare_el3_exit(uint32_t security_state)
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isb();
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} else if (read_id_pfr1() &
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(ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) {
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/* Set the NS bit to access HCR, HCPTR, CNTHCTL, VPIDR, VMPIDR */
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/*
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* Set the NS bit to access NS copies of certain banked
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* registers
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*/
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write_scr(read_scr() | SCR_NS_BIT);
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isb();
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@ -231,6 +234,15 @@ void cm_prepare_el3_exit(uint32_t security_state)
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* translation are disabled.
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*/
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write64_vttbr(0);
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/*
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* Avoid unexpected debug traps in case where HDCR
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* is not completely reset by the hardware - set
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* HDCR.HPMN to PMCR.N and zero the remaining bits.
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* The HDCR.HPMN and PMCR.N fields are the same size
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* (5 bits) and HPMN is at offset zero within HDCR.
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*/
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write_hdcr((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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@ -259,6 +259,16 @@ void cm_prepare_el3_exit(uint32_t security_state)
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* translation are disabled.
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*/
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write_vttbr_el2(0);
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/*
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* Avoid unexpected debug traps in case where MDCR_EL2
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* is not completely reset by the hardware - set
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* MDCR_EL2.HPMN to PMCR_EL0.N and zero the remaining
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* bits.
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* MDCR_EL2.HPMN and PMCR_EL0.N fields are the same size
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* (5 bits) and HPMN is at offset zero within MDCR_EL2.
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*/
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write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS)
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>> PMCR_EL0_N_SHIFT);
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}
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}
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