rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
[IPL/DDR] - Update DDR setting rev.0.35. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
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@ -95,7 +95,6 @@ static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
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static uint32_t max_density;
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static uint32_t ddr0800_mul;
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static uint32_t ddr_mul;
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static uint32_t ddr_mbps;
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static uint32_t DDR_PHY_SLICE_REGSET_OFS;
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static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
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static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
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@ -1136,6 +1135,7 @@ static void regif_pll_wa(void)
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uint32_t ch;
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if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
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// PLL setting for PHY : H3 Ver.1.x
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reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
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(0x0064U <<
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ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
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@ -1175,6 +1175,9 @@ static void regif_pll_wa(void)
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_reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
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}
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reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
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_cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]);
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/* protect register interface */
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ddrphy_regif_idle();
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pll3_control(0);
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@ -1902,7 +1905,14 @@ static void ddr_config(void)
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CACS DLY
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***********************************************************************/
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dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
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set_dfifrequency(0x1f);
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if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
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set_dfifrequency(0x1f);
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} else {
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ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
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ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x01);
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}
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foreach_vch(ch) {
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int16_t adj;
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for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
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@ -1921,7 +1931,13 @@ static void ddr_config(void)
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}
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}
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}
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set_dfifrequency(0x00);
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if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
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set_dfifrequency(0x00);
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} else {
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ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
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ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x00);
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}
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/***********************************************************************
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WDQDM DLY
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@ -2234,7 +2250,16 @@ static void dbsc_regset(void)
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+ (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
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if (tmp[0] < dataL)
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tmp[0] = dataL;
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mmio_write_32(DBSC_DBSCHRW1, tmp[0]);
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if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
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mmio_write_32(DBSC_DBSCHRW1, tmp[0]
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+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
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* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3);
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} else {
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mmio_write_32(DBSC_DBSCHRW1, tmp[0]
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+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
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* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps);
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}
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/***********************************************************************
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QOS and CAM
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@ -2378,6 +2403,38 @@ static void dbsc_regset_post(void)
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dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
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mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff));
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mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
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#ifdef DDR_BACKUPMODE
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if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
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#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
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PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
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send_dbcmd(0x08040001);
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wait_dbcmd();
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send_dbcmd(0x0A040001);
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wait_dbcmd();
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send_dbcmd(0x04040010);
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wait_dbcmd();
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if (Prr_Product == PRR_PRODUCT_H3) {
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send_dbcmd(0x08140001);
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wait_dbcmd();
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send_dbcmd(0x0A140001);
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wait_dbcmd();
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send_dbcmd(0x04140010);
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wait_dbcmd();
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}
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#else /* DDR_BACKUPMODE_HALF //for All channels */
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send_dbcmd(0x08840001);
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wait_dbcmd();
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send_dbcmd(0x0A840001);
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wait_dbcmd();
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send_dbcmd(0x04840010);
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wait_dbcmd();
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#endif /* DDR_BACKUPMODE_HALF */
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}
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#endif /* DDR_BACKUPMODE */
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#if RCAR_REWT_TRAINING != 0
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/* Periodic-WriteDQ Training seeting */
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if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
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@ -2433,37 +2490,6 @@ static void dbsc_regset_post(void)
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#endif /* RCAR_DRAM_SPLIT == 2 */
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}
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#ifdef DDR_BACKUPMODE
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if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
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#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
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PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
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send_dbcmd(0x08040001);
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wait_dbcmd();
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send_dbcmd(0x0A040001);
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wait_dbcmd();
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send_dbcmd(0x04040010);
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wait_dbcmd();
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if (Prr_Product == PRR_PRODUCT_H3) {
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send_dbcmd(0x08140001);
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wait_dbcmd();
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send_dbcmd(0x0A140001);
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wait_dbcmd();
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send_dbcmd(0x04140010);
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wait_dbcmd();
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}
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#else /* DDR_BACKUPMODE_HALF //for All channels */
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send_dbcmd(0x08840001);
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wait_dbcmd();
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send_dbcmd(0x0A840001);
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wait_dbcmd();
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send_dbcmd(0x04840010);
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wait_dbcmd();
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#endif /* DDR_BACKUPMODE_HALF */
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}
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#endif /* DDR_BACKUPMODE */
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mmio_write_32(DBSC_DBRFEN, 0x00000001);
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/* dram access enable */
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mmio_write_32(DBSC_DBACEN, 0x00000001);
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@ -3104,6 +3130,7 @@ static uint32_t init_ddr(void)
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/***********************************************************************
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exec pi_training
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***********************************************************************/
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ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
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ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
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if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
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@ -4,7 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define BOARDNUM 19
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#define BOARDNUM 20
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#define BOARD_JUDGE_AUTO
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#ifdef BOARD_JUDGE_AUTO
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@ -1374,6 +1374,57 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
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}
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}
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},
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/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
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{
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0x03,
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0x01,
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0x02c0,
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0,
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0x0300,
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0x00a0,
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{
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{
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{0x04, 0xff},
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0x00543210,
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0x3201,
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{0x70612543, 0x43251670, 0x45326170, 0x10672534},
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{0x08, 0x08, 0x08, 0x08},
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WDQLVL_PAT,
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0}
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},
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{
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{0x04, 0xff},
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0x00543210,
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0x2310,
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{0x01327654, 0x34526107, 0x35421670, 0x70615324},
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{0x08, 0x08, 0x08, 0x08},
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WDQLVL_PAT,
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0}
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}
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}
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},
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};
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void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
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} else if (Prr_Product == PRR_PRODUCT_M3N) {
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/* RENESAS SALVATOR-X (M3-N/SIP) */
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brd = 11;
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} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
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} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) {
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/* RENESAS SALVATOR-X (M3-W/SIP) */
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brd = 0;
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} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
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/* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */
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brd = 19;
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} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
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/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
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brd = 18;
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@ -1,10 +1,10 @@
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RCAR_DDR_VERSION "rev.0.35rc01"
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#define RCAR_DDR_VERSION "rev.0.35"
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#define DRAM_CH_CNT (0x04)
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#define SLICE_CNT (0x04)
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#define CS_CNT (0x02)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -239,8 +239,8 @@ static const uint32_t
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/*069d*/ 0x0002c000,
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/*069e*/ 0x02c002c0,
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/*069f*/ 0x000002c0,
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/*06a0*/ 0x01421142,
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/*06a1*/ 0x00000142,
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/*06a0*/ 0x03421342,
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/*06a1*/ 0x00000342,
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/*06a2*/ 0x00000000,
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/*06a3*/ 0x00000000,
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/*06a4*/ 0x05020000,
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -219,8 +219,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
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/*0b95*/ 0x0002c000,
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/*0b96*/ 0x02c002c0,
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/*0b97*/ 0x000002c0,
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/*0b98*/ 0x01421142,
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/*0b99*/ 0x00000142,
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/*0b98*/ 0x03421342,
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/*0b99*/ 0x00000342,
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/*0b9a*/ 0x00000000,
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/*0b9b*/ 0x00000000,
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/*0b9c*/ 0x05020000,
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*0b9e*/ 0x02c002c0,
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/*0b9f*/ 0x000002c0,
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/*0ba0*/ 0x08040201,
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/*0ba1*/ 0x01421142,
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/*0ba2*/ 0x00000142,
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/*0ba1*/ 0x03421342,
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/*0ba2*/ 0x00000342,
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/*0ba3*/ 0x00000000,
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/*0ba4*/ 0x00000000,
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/*0ba5*/ 0x05030000,
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