feat(morello): add changes to enable TBBR boot
This patch adds all SOC and FVP related changes required to boot a standard TBBR style boot on Morello. Signed-off-by: sahil <sahil@arm.com> Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c
This commit is contained in:
Manoj Kumar
Chandni Cherukuri
parent
572c8ce255
commit
4af5397753
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@ -0,0 +1,20 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x200>;
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id = <TB_FW_CONFIG_ID>;
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};
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};
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};
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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tb_fw-config {
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compatible = "arm,tb_fw";
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* The following two entries are placeholders for Mbed TLS
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* heap information. The default values don't matter since
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* they will be overwritten by BL1.
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* In case of having shared Mbed TLS heap between BL1 and BL2,
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* BL1 will populate these two properties with the respective
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* info about the shared heap. This info will be available for
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* BL2 in order to locate and re-use the heap.
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*/
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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};
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -24,6 +24,30 @@
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#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
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#define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define PLAT_ARM_FLASH_IMAGE_BASE ULL(0x1A000000)
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE ULL(0x01000000)
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#define PLAT_ARM_NVM_BASE ULL(0x1A000000)
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#define PLAT_ARM_NVM_SIZE ULL(0x01000000)
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#if defined NS_BL1U_BASE
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#undef NS_BL1U_BASE
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#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000))
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#endif
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/*
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* There are no non-volatile counters in morello, these macros points
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* to unused addresses.
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*/
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#define SOC_TRUSTED_NVCTR_BASE ULL(0x7FE70000)
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#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0000))
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#define TFW_NVCTR_SIZE U(4)
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#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0004))
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#define NTFW_CTR_SIZE U(4)
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/*
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* To access the complete DDR memory along with remote chip's DDR memory,
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* which is at 4 TB offset, physical and virtual address space limits are
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@ -39,7 +63,36 @@
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#endif
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#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000)
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x20000)
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xE000)
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
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#else
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# define PLAT_ARM_MAX_BL2_SIZE UL(0x14000)
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#endif
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
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/*******************************************************************************
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* MORELLO topology related constants
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@ -62,12 +115,49 @@
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#define PLAT_ARM_MMAP_ENTRIES U(9)
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#define MAX_XLAT_TABLES U(10)
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#if IMAGE_BL1 || IMAGE_BL31
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# define PLAT_ARM_MMAP_ENTRIES U(6)
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# define MAX_XLAT_TABLES U(7)
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#else
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# define PLAT_ARM_MMAP_ENTRIES U(5)
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# define MAX_XLAT_TABLES U(6)
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#endif
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#define PLATFORM_STACK_SIZE U(0x400)
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE UL(0x1000)
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# else
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# define PLATFORM_STACK_SIZE UL(0x440)
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# endif
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#elif defined(IMAGE_BL2)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE UL(0x1000)
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# else
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# define PLATFORM_STACK_SIZE UL(0x400)
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# endif
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#elif defined(IMAGE_BL2U)
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# define PLATFORM_STACK_SIZE UL(0x400)
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#elif defined(IMAGE_BL31)
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# if SPM_MM
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# define PLATFORM_STACK_SIZE UL(0x500)
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# else
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# define PLATFORM_STACK_SIZE UL(0x400)
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# endif
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#elif defined(IMAGE_BL32)
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# define PLATFORM_STACK_SIZE UL(0x440)
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#endif
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#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
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#define PLAT_ARM_TRUSTED_ROM_BASE U(0x0)
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#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) /* 128KB */
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#define PLAT_ARM_NSRAM_BASE ULL(0x06000000)
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#define PLAT_ARM_NSRAM_SIZE UL(0x00010000) /* 64KB */
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#define PLAT_CSS_MHU_BASE UL(0x45000000)
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#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
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#define PLAT_MAX_PWR_LVL U(2)
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#define MORELLO_DEVICE_BASE ULL(0x08000000)
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#define MORELLO_DEVICE_SIZE ULL(0x48000000)
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/*Secure Watchdog Constants */
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#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
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#define SBSA_SECURE_WDOG_TIMEOUT UL(1000)
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#define MORELLO_MAP_DEVICE MAP_REGION_FLAT( \
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MORELLO_DEVICE_BASE, \
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MORELLO_DEVICE_SIZE, \
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void soc_css_init_nic400(void)
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{
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}
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void soc_css_init_pcie(void)
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{
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}
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/utils.h>
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#include <plat/arm/common/plat_arm.h>
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void bl2_platform_setup(void)
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{
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#ifdef TARGET_PLATFORM_SOC
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/*
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* Morello platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC-Bing.
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* Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage,
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* as BL33 binary cannot be copied to DDR memory before enabling ECC.
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* Rest of the DDR memory space is zeroed out during BL31 stage.
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*/
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INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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#endif
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arm_bl2_platform_setup();
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}
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@ -36,16 +36,6 @@ struct morello_plat_info {
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/* Compile time assertion to ensure the size of structure is 18 bytes */
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CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE,
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assert_invalid_plat_info_size);
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/*
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* BL33 image information structure stored in SDS.
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* This structure holds the source & destination addresses and
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* the size of the BL33 image which will be loaded by BL31.
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*/
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struct morello_bl33_info {
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uint32_t bl33_src_addr;
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uint32_t bl33_dst_addr;
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uint32_t bl33_size;
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};
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static scmi_channel_plat_info_t morello_scmi_plat_info = {
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.scmi_mbx_mem = MORELLO_SCMI_PAYLOAD_BASE,
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@ -72,9 +62,7 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
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* enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of
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* memory from SCP is quite time consuming so the following function
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* is added to zero out the DDR memory from application processor which is
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* much faster compared to SCP. BL33 binary cannot be copied to DDR memory
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* before enabling ECC so copy_bl33 function is added to copy BL33 binary
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* from IOFPGA-DDR3 memory to main DDR4 memory.
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* much faster compared to SCP.
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*/
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static void dmc_ecc_setup(struct morello_plat_info *plat_info)
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@ -90,9 +78,8 @@ static void dmc_ecc_setup(struct morello_plat_info *plat_info)
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assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE);
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dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE;
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VERBOSE("Zeroing DDR memories\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n",
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ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size);
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zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size);
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flush_dcache_range(ARM_DRAM2_BASE, dram2_size);
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@ -201,28 +188,10 @@ static void dmc_ecc_setup(struct morello_plat_info *plat_info)
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}
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#endif
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static void copy_bl33(uint32_t src, uint32_t dst, uint32_t size)
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{
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unsigned int i;
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INFO("Copying BL33 to DDR memory...\n");
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for (i = 0U; i < size; (i = i + 8U))
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mmio_write_64((dst + i), mmio_read_64(src + i));
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for (i = 0U; i < size; (i = i + 8U)) {
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if (mmio_read_64(src + i) != mmio_read_64(dst + i)) {
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ERROR("Copy failed!\n");
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panic();
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}
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}
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INFO("done\n");
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}
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void bl31_platform_setup(void)
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{
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int ret;
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struct morello_plat_info plat_info;
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struct morello_bl33_info bl33_info;
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struct morello_plat_info *copy_dest;
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ret = sds_init();
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@ -256,18 +225,6 @@ void bl31_platform_setup(void)
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dmc_ecc_setup(&plat_info);
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#endif
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ret = sds_struct_read(MORELLO_SDS_BL33_INFO_STRUCT_ID,
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MORELLO_SDS_BL33_INFO_OFFSET,
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&bl33_info,
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MORELLO_SDS_BL33_INFO_SIZE,
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SDS_ACCESS_MODE_NON_CACHED);
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if (ret != SDS_OK) {
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ERROR("Error getting BL33 info from SDS. ret:%d\n", ret);
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panic();
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}
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copy_bl33(bl33_info.bl33_src_addr,
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bl33_info.bl33_dst_addr,
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bl33_info.bl33_size);
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/*
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* Pass platform information to BL33. This method is followed as
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* currently there is no BL1/BL2 involved in boot flow of MORELLO.
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@ -22,11 +22,6 @@
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#define MORELLO_MAX_DDR_CAPACITY U(0x1000000000)
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#define MORELLO_MAX_SLAVE_COUNT U(16)
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/* SDS BL33 image information defines */
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#define MORELLO_SDS_BL33_INFO_STRUCT_ID U(9)
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#define MORELLO_SDS_BL33_INFO_OFFSET U(0)
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#define MORELLO_SDS_BL33_INFO_SIZE U(12)
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#define MORELLO_SCC_SERVER_MODE U(0)
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#define MORELLO_SCC_CLIENT_MODE_MASK U(1)
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#define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4)
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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/*
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* morello error handler
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*/
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void __dead2 plat_arm_error_handler(int err)
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{
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while (true) {
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wfi();
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}
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}
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@ -4,6 +4,9 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/arm/sbsa.h>
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#include <plat/arm/common/plat_arm.h>
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#include "morello_def.h"
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@ -12,7 +15,7 @@
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* Table of regions to map using the MMU.
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* Replace or extend the below regions as required
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*/
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#if IMAGE_BL1 || IMAGE_BL31
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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MORELLO_MAP_DEVICE,
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@ -21,3 +24,36 @@ const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_DRAM2,
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{0}
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};
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#endif
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#if IMAGE_BL2
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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MORELLO_MAP_DEVICE,
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MORELLO_MAP_NS_SRAM,
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ARM_MAP_DRAM1,
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#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
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ARM_MAP_BL1_RW,
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#endif
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{0}
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};
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#endif
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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void plat_arm_secure_wdt_start(void)
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{
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sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
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}
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@ -0,0 +1,54 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <plat/arm/common/plat_arm.h>
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/*
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* Return the non-volatile counter value stored in the platform. The cookie
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* will contain the OID of the counter in the certificate.
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*
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* Return: 0 = success, Otherwise = error
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*/
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int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
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{
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*nv_ctr = MORELLO_FW_NVCTR_VAL;
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return 0;
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}
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/*
|
||||
* Store a new non-volatile counter value. By default on ARM development
|
||||
* platforms, the non-volatile counters are RO and cannot be modified. We expect
|
||||
* the values in the certificates to always match the RO values so that this
|
||||
* function is never called.
|
||||
*
|
||||
* Return: 0 = success, Otherwise = error
|
||||
*/
|
||||
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the ROTPK hash in the following ASN.1 structure in DER format:
|
||||
*
|
||||
* AlgorithmIdentifier ::= SEQUENCE {
|
||||
* algorithm OBJECT IDENTIFIER,
|
||||
* parameters ANY DEFINED BY algorithm OPTIONAL
|
||||
* }
|
||||
*
|
||||
* DigestInfo ::= SEQUENCE {
|
||||
* digestAlgorithm AlgorithmIdentifier,
|
||||
* digest OCTET STRING
|
||||
* }
|
||||
*/
|
||||
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
|
||||
unsigned int *flags)
|
||||
{
|
||||
return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
|
||||
}
|
||||
|
|
@ -30,6 +30,19 @@ MORELLO_GIC_SOURCES := ${GICV3_SOURCES} \
|
|||
PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \
|
||||
${MORELLO_BASE}/aarch64/morello_helper.S
|
||||
|
||||
BL1_SOURCES := ${MORELLO_CPU_SOURCES} \
|
||||
${INTERCONNECT_SOURCES} \
|
||||
${MORELLO_BASE}/morello_err.c \
|
||||
${MORELLO_BASE}/morello_trusted_boot.c \
|
||||
${MORELLO_BASE}/morello_bl1_setup.c \
|
||||
drivers/arm/sbsa/sbsa.c
|
||||
|
||||
BL2_SOURCES := ${MORELLO_BASE}/morello_security.c \
|
||||
${MORELLO_BASE}/morello_err.c \
|
||||
${MORELLO_BASE}/morello_trusted_boot.c \
|
||||
lib/utils/mem_region.c \
|
||||
${MORELLO_BASE}/morello_bl2_setup.c
|
||||
|
||||
BL31_SOURCES := ${MORELLO_CPU_SOURCES} \
|
||||
${INTERCONNECT_SOURCES} \
|
||||
${MORELLO_GIC_SOURCES} \
|
||||
|
|
@ -38,19 +51,27 @@ BL31_SOURCES := ${MORELLO_CPU_SOURCES} \
|
|||
${MORELLO_BASE}/morello_security.c \
|
||||
drivers/arm/css/sds/sds.c
|
||||
|
||||
FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts
|
||||
FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts \
|
||||
${MORELLO_BASE}/fdts/morello_fw_config.dts \
|
||||
${MORELLO_BASE}/fdts/morello_tb_fw_config.dts \
|
||||
|
||||
FW_CONFIG := ${BUILD_PLAT}/fdts/morello_fw_config.dtb
|
||||
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_tb_fw_config.dtb
|
||||
|
||||
# Add the FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
|
||||
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
|
||||
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
|
||||
|
||||
MORELLO_FW_NVCTR_VAL := 0
|
||||
TFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL}
|
||||
NTFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL}
|
||||
|
||||
# TF-A not required to load the SCP Images
|
||||
override CSS_LOAD_SCP_IMAGES := 0
|
||||
|
||||
# BL1/BL2 Image not a part of the capsule Image for morello
|
||||
override NEED_BL1 := no
|
||||
override NEED_BL2 := no
|
||||
override NEED_BL2U := no
|
||||
|
||||
#TF-A for morello starts from BL31
|
||||
override RESET_TO_BL31 := 1
|
||||
|
||||
# 32 bit mode not supported
|
||||
override CTX_INCLUDE_AARCH32_REGS := 0
|
||||
|
||||
|
|
@ -70,6 +91,9 @@ USE_COHERENT_MEM := 0
|
|||
# Add TARGET_PLATFORM to differentiate between Morello FVP and Morello SoC platform
|
||||
$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
|
||||
|
||||
# Add MORELLO_FW_NVCTR_VAL
|
||||
$(eval $(call add_define,MORELLO_FW_NVCTR_VAL))
|
||||
|
||||
include plat/arm/common/arm_common.mk
|
||||
include plat/arm/css/common/css_common.mk
|
||||
include plat/arm/board/common/board_common.mk
|
||||
|
|
|
|||
Loading…
Reference in New Issue