Merge pull request #570 from davwan01/bl31-in-dram
Add support to load BL31 in DRAM
This commit is contained in:
commit
4c51badfb5
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@ -498,6 +498,12 @@ map is explained in the [Firmware Design].
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that wish to optimise memory usage for page tables need to set this flag to 1
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that wish to optimise memory usage for page tables need to set this flag to 1
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and must override the related macros.
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and must override the related macros.
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* 'ARM_BL31_IN_DRAM': Boolean option to select loading of BL31 in TZC secured
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DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
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BL31 in TZC secured DRAM. If TSP is present, then setting this option also
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sets the TSP location to DRAM and ignores the `ARM_TSP_RAM_LOCATION` build
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flag.
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#### ARM CSS platform specific build options
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#### ARM CSS platform specific build options
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* `CSS_DETECT_PRE_1_7_0_SCP`: Boolean flag to detect SCP version
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* `CSS_DETECT_PRE_1_7_0_SCP`: Boolean flag to detect SCP version
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@ -75,10 +75,10 @@
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*/
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*/
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#if IMAGE_BL31 || IMAGE_BL32
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#if IMAGE_BL31 || IMAGE_BL32
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# define PLAT_ARM_MMAP_ENTRIES 6
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# define PLAT_ARM_MMAP_ENTRIES 6
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# define MAX_XLAT_TABLES 3
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#else
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# define PLAT_ARM_MMAP_ENTRIES 9
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# define MAX_XLAT_TABLES 4
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# define MAX_XLAT_TABLES 4
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#else
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# define PLAT_ARM_MMAP_ENTRIES 10
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# define MAX_XLAT_TABLES 5
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#endif
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MMAP */
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#endif /* ARM_BOARD_OPTIMISE_MMAP */
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@ -165,6 +165,12 @@
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TSP_SEC_MEM_SIZE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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MT_MEMORY | MT_RW | MT_SECURE)
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#if ARM_BL31_IN_DRAM
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#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
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BL31_BASE, \
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PLAT_ARM_MAX_BL31_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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/*
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/*
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* The number of regions like RO(code), coherent and data required by
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* The number of regions like RO(code), coherent and data required by
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@ -240,15 +246,32 @@
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/*******************************************************************************
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/*******************************************************************************
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* BL2 specific defines.
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* BL2 specific defines.
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******************************************************************************/
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******************************************************************************/
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#if ARM_BL31_IN_DRAM
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/*
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* BL31 is loaded in the DRAM.
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* Put BL2 just below BL1.
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*/
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#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL1_RW_BASE
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#else
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/*
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/*
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* Put BL2 just below BL31.
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* Put BL2 just below BL31.
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*/
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*/
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#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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#define BL2_LIMIT BL31_BASE
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#endif
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/*******************************************************************************
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/*******************************************************************************
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* BL31 specific defines.
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* BL31 specific defines.
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******************************************************************************/
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******************************************************************************/
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#if ARM_BL31_IN_DRAM
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/*
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* Put BL31 at the bottom of TZC secured DRAM
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*/
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#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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#else
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/*
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/*
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* Put BL31 at the top of the Trusted SRAM.
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* Put BL31 at the top of the Trusted SRAM.
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*/
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*/
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@ -257,6 +280,7 @@
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PLAT_ARM_MAX_BL31_SIZE)
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PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#endif
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/*******************************************************************************
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/*******************************************************************************
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* BL32 specific defines.
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* BL32 specific defines.
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@ -266,7 +290,16 @@
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* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
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* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
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* controller.
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* controller.
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*/
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*/
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#if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
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#if ARM_BL31_IN_DRAM
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# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
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PLAT_ARM_MAX_BL31_SIZE)
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# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE)
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#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
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# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
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# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
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# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
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# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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@ -292,7 +325,11 @@
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* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
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* FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
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******************************************************************************/
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******************************************************************************/
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#define BL2U_BASE BL2_BASE
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#define BL2U_BASE BL2_BASE
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#if ARM_BL31_IN_DRAM
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#define BL2U_LIMIT BL1_RW_BASE
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#else
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#define BL2U_LIMIT BL31_BASE
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#define BL2U_LIMIT BL31_BASE
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#endif
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#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
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#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
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#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
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#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
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@ -97,6 +97,9 @@ const mmap_region_t plat_arm_mmap[] = {
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MAP_DEVICE2,
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MAP_DEVICE2,
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ARM_MAP_NS_DRAM1,
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ARM_MAP_NS_DRAM1,
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ARM_MAP_TSP_SEC_MEM,
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ARM_MAP_TSP_SEC_MEM,
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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{0}
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{0}
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};
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};
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#endif
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#endif
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@ -146,11 +146,7 @@
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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* plus a little space for growth.
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*/
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*/
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#if TRUSTED_BOARD_BOOT
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#define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000
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#else
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# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
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#endif
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/*
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* modification, are permitted provided that the following conditions are met:
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@ -96,11 +96,27 @@ static bl2_to_bl31_params_mem_t bl31_params_mem;
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#pragma weak bl2_plat_get_bl33_meminfo
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#pragma weak bl2_plat_get_bl33_meminfo
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#pragma weak bl2_plat_set_bl33_ep_info
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#pragma weak bl2_plat_set_bl33_ep_info
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#if ARM_BL31_IN_DRAM
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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static meminfo_t bl2_dram_layout
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__aligned(CACHE_WRITEBACK_GRANULE) = {
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.total_base = BL31_BASE,
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.total_size = (ARM_AP_TZC_DRAM1_BASE +
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ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
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.free_base = BL31_BASE,
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.free_size = (ARM_AP_TZC_DRAM1_BASE +
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ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
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};
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return &bl2_dram_layout;
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}
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#else
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meminfo_t *bl2_plat_sec_mem_layout(void)
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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{
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return &bl2_tzram_layout;
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return &bl2_tzram_layout;
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}
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}
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#endif
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/*******************************************************************************
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/*******************************************************************************
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* This function assigns a pointer to the memory that the platform has kept
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* This function assigns a pointer to the memory that the platform has kept
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@ -77,6 +77,11 @@ ARM_CONFIG_CNTACR := 1
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$(eval $(call assert_boolean,ARM_CONFIG_CNTACR))
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$(eval $(call assert_boolean,ARM_CONFIG_CNTACR))
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$(eval $(call add_define,ARM_CONFIG_CNTACR))
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$(eval $(call add_define,ARM_CONFIG_CNTACR))
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# Process ARM_BL31_IN_DRAM flag
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ARM_BL31_IN_DRAM := 0
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$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
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$(eval $(call add_define,ARM_BL31_IN_DRAM))
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PLAT_INCLUDES += -Iinclude/common/tbbr \
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PLAT_INCLUDES += -Iinclude/common/tbbr \
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-Iinclude/plat/arm/common \
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-Iinclude/plat/arm/common \
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-Iinclude/plat/arm/common/aarch64
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-Iinclude/plat/arm/common/aarch64
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