Merge pull request #554 from ljerry/tf_issue_368_ter
Enable asynchronous abort exceptions during boot
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commit
aaa416a462
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@ -38,7 +38,7 @@
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void bl1_arch_setup(void)
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{
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/* Set the next EL to be AArch64 */
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write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT);
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write_scr_el3(read_scr_el3() | SCR_RW_BIT);
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}
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/*******************************************************************************
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@ -43,9 +43,6 @@
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******************************************************************************/
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void bl31_arch_setup(void)
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{
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/* Set the RES1 bits in the SCR_EL3 */
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write_scr_el3(SCR_RES1_BITS);
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/* Program the counter frequency */
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write_cntfrq_el0(plat_get_syscnt_freq());
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@ -70,7 +70,8 @@ non_el3_sys_regs:
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"tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\
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"mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\
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"vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\
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"cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", ""
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"cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\
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"isr_el1", ""
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panic_msg:
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.asciz "PANIC in EL3 at x30 = 0x"
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@ -338,6 +339,7 @@ func do_crash_reporting
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mrs x8, cntkctl_el1
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mrs x9, fpexc32_el2
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mrs x10, sp_el0
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mrs x11, isr_el1
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bl str_in_crash_buf_print
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/* Get the cpu specific registers to report */
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@ -111,6 +111,11 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t
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if (EP_GET_ST(ep->h.attr))
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scr_el3 |= SCR_ST_BIT;
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#ifndef HANDLE_EA_EL3_FIRST
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/* Explicitly stop to trap aborts from lower exception levels. */
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scr_el3 &= ~SCR_EA_BIT;
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#endif
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#if IMAGE_BL31
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/*
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* IRQ/FIQ bits only need setting if interrupt routing
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@ -174,8 +174,9 @@ BL1 performs minimal architectural initialization as follows.
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`SCTLR_EL3.A` and `SCTLR_EL3.SA` bits. Exception endianness is set to
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little-endian by clearing the `SCTLR_EL3.EE` bit.
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- `SCR_EL3`. The register width of the next lower exception level is set to
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AArch64 by setting the `SCR.RW` bit.
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- `SCR_EL3`. The register width of the next lower exception level is set
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to AArch64 by setting the `SCR.RW` bit. The `SCR.EA` bit is set to trap
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both External Aborts and SError Interrupts in EL3.
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- `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the
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`CPTR_EL2` register from EL2 are configured to not trap to EL3 by
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@ -439,6 +439,9 @@ performed.
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where applicable). Defaults to a string that contains the time and date of
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the compilation.
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* `HANDLE_EA_EL3_FIRST`: When defined External Aborts and SError Interrupts
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will be always trapped in EL3 i.e. in BL31 at runtime.
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#### ARM development platform specific build options
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* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options:
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@ -70,8 +70,15 @@
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isb
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/* ---------------------------------------------------------------------
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* Enable the SError interrupt now that the exception vectors have been
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* setup.
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* Early set RES1 bits in SCR_EL3. Set EA bit as well to catch both
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* External Aborts and SError Interrupts in EL3.
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* ---------------------------------------------------------------------
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*/
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mov x0, #(SCR_RES1_BITS | SCR_EA_BIT)
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msr scr_el3, x0
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/* ---------------------------------------------------------------------
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* Enable External Aborts and SError Interrupts now that the exception
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* vectors have been setup.
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* ---------------------------------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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@ -186,6 +186,11 @@
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#define HCR_IMO_BIT (1 << 4)
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#define HCR_FMO_BIT (1 << 3)
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/* ISR definitions */
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#define ISR_A_SHIFT 8
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#define ISR_I_SHIFT 7
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#define ISR_F_SHIFT 6
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/* CNTHCTL_EL2 definitions */
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#define EVNTEN_BIT (1 << 2)
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#define EL1PCEN_BIT (1 << 1)
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@ -168,15 +168,6 @@ void disable_mmu_icache_el3(void);
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DEFINE_SYSREG_WRITE_CONST_FUNC(daifset)
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DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr)
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#define enable_irq() write_daifclr(DAIF_IRQ_BIT)
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#define enable_fiq() write_daifclr(DAIF_FIQ_BIT)
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#define enable_serror() write_daifclr(DAIF_ABT_BIT)
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#define enable_debug_exceptions() write_daifclr(DAIF_DBG_BIT)
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#define disable_irq() write_daifset(DAIF_IRQ_BIT)
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#define disable_fiq() write_daifset(DAIF_FIQ_BIT)
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#define disable_serror() write_daifset(DAIF_ABT_BIT)
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#define disable_debug_exceptions() write_daifset(DAIF_DBG_BIT)
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DEFINE_SYSREG_READ_FUNC(par_el1)
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DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
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