Tegra: common: fix defects flagged by MISRA scan
Macro assert(e) request 'e' is a bool type, if useing other type, MISRA report a "The Essential Type Model" violation, Add a judgement to fix the defects, if 'e' is not bool type. Remove unused code [Rule 2.5] Fix the essential type model violation [Rule 10.6, 10.7] Use local parameter to raplace function parameter [Rule 17.8] Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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@ -293,7 +293,7 @@ static void tegra_memctrl_set_overrides(void)
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uint32_t i, val;
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/* Get the settings from the platform */
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assert(plat_mc_settings);
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assert(plat_mc_settings != NULL);
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mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
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num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
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@ -357,7 +357,7 @@ void tegra_memctrl_setup(void)
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tegra_smmu_init();
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#endif
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/* Get the settings from the platform */
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assert(plat_mc_settings);
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assert(plat_mc_settings != NULL);
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mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
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num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
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mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
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@ -94,7 +94,7 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
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/* get SMMU context table */
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smmu_ctx_regs = plat_get_smmu_ctx();
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assert(smmu_ctx_regs);
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assert(smmu_ctx_regs != NULL);
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/*
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* smmu_ctx_regs[0].val contains the size of the context table minus
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@ -143,8 +143,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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assert(arg_from_bl2);
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assert(arg_from_bl2->bl33_ep_info);
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assert(arg_from_bl2 != NULL);
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assert(arg_from_bl2->bl33_ep_info != NULL);
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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if (arg_from_bl2->bl32_ep_info != NULL) {
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@ -156,7 +156,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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/*
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* Parse platform specific parameters - TZDRAM aperture base and size
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*/
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assert(plat_params);
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assert(plat_params != NULL);
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plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
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plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
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plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
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@ -65,7 +65,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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* Set the new ELR to continue execution in the NS world using the
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* FIQ handler registered earlier.
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*/
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assert(ns_fiq_handler_addr);
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assert(ns_fiq_handler_addr != 0ULL);
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write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr));
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/*
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@ -15,7 +15,7 @@
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* Tegra platforms
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******************************************************************************/
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typedef enum tegra_platform {
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TEGRA_PLATFORM_SILICON = 0,
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TEGRA_PLATFORM_SILICON = 0U,
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TEGRA_PLATFORM_QT,
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TEGRA_PLATFORM_FPGA,
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TEGRA_PLATFORM_EMULATION,
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@ -83,7 +83,7 @@ bool tegra_chipid_is_t132(void)
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{
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uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
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return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA13);
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return (chip_id == TEGRA_CHIPID_TEGRA13);
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}
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bool tegra_chipid_is_t186(void)
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@ -97,12 +97,12 @@ bool tegra_chipid_is_t210(void)
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{
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uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
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return (chip_id == (uint32_t)TEGRA_CHIPID_TEGRA21);
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return (chip_id == TEGRA_CHIPID_TEGRA21);
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}
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bool tegra_chipid_is_t210_b01(void)
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{
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return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2UL));
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return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U));
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}
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/*
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@ -106,7 +106,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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(void)lvl;
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assert(ncpu);
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assert(ncpu != 0U);
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do {
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temp = *local_state;
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@ -335,7 +335,7 @@ __dead2 void tegra_system_reset(void)
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int32_t tegra_validate_power_state(uint32_t power_state,
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psci_power_state_t *req_state)
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{
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assert(req_state);
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assert(req_state != NULL);
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return tegra_soc_validate_power_state(power_state, req_state);
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}
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@ -69,7 +69,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
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void *handle,
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u_register_t flags)
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{
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uint32_t regval;
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uint32_t regval, local_x2_32 = (uint32_t)x2;
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int32_t err;
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/* Check if this is a SoC specific SiP */
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@ -84,14 +84,11 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* clean up the high bits */
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x2 = (uint32_t)x2;
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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*/
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err = bl31_check_ns_address(x1, x2);
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err = bl31_check_ns_address(x1, local_x2_32);
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if (err != 0) {
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SMC_RET1(handle, (uint64_t)err);
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}
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@ -99,7 +96,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
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/*
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* Check if Video Memory is aligned to 1MB.
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*/
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if (((x1 & 0xFFFFFU) != 0U) || ((x2 & 0xFFFFFU) != 0U)) {
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if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
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ERROR("Unaligned Video Memory base address!\n");
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SMC_RET1(handle, -ENOTSUP);
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}
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@ -117,7 +114,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
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}
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/* new video memory carveout settings */
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tegra_memctrl_videomem_setup(x1, (uint32_t)x2);
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tegra_memctrl_videomem_setup(x1, local_x2_32);
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SMC_RET1(handle, 0);
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