rockchip: fixes the clock select and divide register for rk3399
As the new RK3399TRM v1.1, there are some wrong set for CRU_CLKSEL_CON register. As the CRU_CLKSEL_CON96~107 high 16-bit isn't write mask and the CRU_CLKSEL_CON offset is 0x100,not 0x80. Change-Id: Ie127e9de74b87100af9a0150aad43e89e4972529
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@ -325,9 +325,16 @@ void plls_resume_finish(void)
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{
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{
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int i;
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int i;
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for (i = 0; i < CRU_CLKSEL_COUNT; i++)
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for (i = 0; i < CRU_CLKSEL_COUNT; i++) {
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mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)),
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/* CRU_CLKSEL_CON96~107 the high 16-bit isb't write_mask */
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REG_SOC_WMSK | slp_data.cru_clksel_con[i]);
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if (i > 95)
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mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)),
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slp_data.cru_clksel_con[i]);
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else
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mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)),
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REG_SOC_WMSK |
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slp_data.cru_clksel_con[i]);
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}
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for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++)
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for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++)
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mmio_write_32((PMUCRU_BASE +
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mmio_write_32((PMUCRU_BASE +
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PMUCRU_CLKSEL_OFFSET + i * REG_SIZE),
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PMUCRU_CLKSEL_OFFSET + i * REG_SIZE),
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@ -65,7 +65,7 @@
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#define PLL_CON_COUNT 0x06
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#define PLL_CON_COUNT 0x06
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#define CRU_CLKSEL_COUNT 0x108
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#define CRU_CLKSEL_COUNT 0x108
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#define CRU_CLKSEL_CON(n) (0x80 + (n) * 4)
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#define CRU_CLKSEL_CON(n) (0x100 + (n) * 4)
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#define PMUCRU_CLKSEL_CONUT 0x06
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#define PMUCRU_CLKSEL_CONUT 0x06
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#define PMUCRU_CLKSEL_OFFSET 0x080
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#define PMUCRU_CLKSEL_OFFSET 0x080
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