Merge changes from topic "my-topic-name" into integration
* changes: plat: imx8mm: Add image load logic for TBBR FIP booting plat: imx8mm: Add initial defintions to facilitate FIP layout plat: imx8mm: Add image io-storage logic for TBBR FIP booting plat: imx8mm: Add imx8mm_private.h to the build
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
51672950ee
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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void plat_flush_next_bl_params(void)
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{
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flush_bl_params_desc();
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}
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bl_load_info_t *plat_get_bl_image_load_info(void)
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{
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return get_bl_load_info_from_mem_params_desc();
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}
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bl_params_t *plat_get_next_bl_params(void)
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{
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return get_next_bl_params_from_mem_params_desc();
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}
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/io/io_block.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_fip.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_memmap.h>
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#include <drivers/mmc.h>
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#include <lib/utils_def.h>
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#include <tbbr_img_def.h>
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#include <tools_share/firmware_image_package.h>
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#include <platform_def.h>
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static const io_dev_connector_t *fip_dev_con;
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static uintptr_t fip_dev_handle;
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#ifndef IMX8MM_FIP_MMAP
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static const io_dev_connector_t *mmc_dev_con;
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static uintptr_t mmc_dev_handle;
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static const io_block_spec_t mmc_fip_spec = {
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.offset = IMX8MM_FIP_MMC_BASE,
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.length = IMX8MM_FIP_SIZE
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};
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static const io_block_dev_spec_t mmc_dev_spec = {
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/* It's used as temp buffer in block driver. */
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.buffer = {
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.offset = IMX8MM_FIP_BASE,
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/* do we need a new value? */
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.length = IMX8MM_FIP_SIZE
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},
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.ops = {
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.read = mmc_read_blocks,
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.write = mmc_write_blocks,
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},
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.block_size = MMC_BLOCK_SIZE,
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};
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static int open_mmc(const uintptr_t spec);
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#else
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static const io_dev_connector_t *memmap_dev_con;
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static uintptr_t memmap_dev_handle;
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static const io_block_spec_t fip_block_spec = {
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.offset = IMX8MM_FIP_BASE,
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.length = IMX8MM_FIP_SIZE
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};
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static int open_memmap(const uintptr_t spec);
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#endif
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static int open_fip(const uintptr_t spec);
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static const io_uuid_spec_t bl31_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
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};
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static const io_uuid_spec_t bl32_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32,
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};
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static const io_uuid_spec_t bl32_extra1_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
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};
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static const io_uuid_spec_t bl32_extra2_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
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};
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static const io_uuid_spec_t bl33_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
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};
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#if TRUSTED_BOARD_BOOT
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static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_BOOT_FW_CERT,
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};
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static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_KEY_CERT,
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};
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static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
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.uuid = UUID_SOC_FW_KEY_CERT,
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};
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static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
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};
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static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t soc_fw_content_cert_uuid_spec = {
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.uuid = UUID_SOC_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
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};
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static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
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};
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#endif /* TRUSTED_BOARD_BOOT */
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struct plat_io_policy {
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uintptr_t *dev_handle;
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uintptr_t image_spec;
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int (*check)(const uintptr_t spec);
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};
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static const struct plat_io_policy policies[] = {
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#ifndef IMX8MM_FIP_MMAP
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[FIP_IMAGE_ID] = {
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&mmc_dev_handle,
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(uintptr_t)&mmc_fip_spec,
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open_mmc
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},
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#else
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[FIP_IMAGE_ID] = {
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&memmap_dev_handle,
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(uintptr_t)&fip_block_spec,
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open_memmap
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},
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#endif
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[BL31_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl31_uuid_spec,
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open_fip
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},
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[BL32_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_uuid_spec,
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open_fip
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},
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[BL32_EXTRA1_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_extra1_uuid_spec,
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open_fip
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},
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[BL32_EXTRA2_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_extra2_uuid_spec,
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open_fip
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},
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[BL33_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl33_uuid_spec,
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open_fip
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},
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#if TRUSTED_BOARD_BOOT
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[TRUSTED_BOOT_FW_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tb_fw_cert_uuid_spec,
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open_fip
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},
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[SOC_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&soc_fw_key_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&trusted_key_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_OS_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tos_fw_key_cert_uuid_spec,
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open_fip
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},
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[NON_TRUSTED_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&nt_fw_key_cert_uuid_spec,
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open_fip
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},
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[SOC_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&soc_fw_content_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&tos_fw_cert_uuid_spec,
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open_fip
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},
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[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&nt_fw_cert_uuid_spec,
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open_fip
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},
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#endif /* TRUSTED_BOARD_BOOT */
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};
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static int open_fip(const uintptr_t spec)
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{
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int result;
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uintptr_t local_image_handle;
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/* See if a Firmware Image Package is available */
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result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
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if (result == 0) {
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result = io_open(fip_dev_handle, spec, &local_image_handle);
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if (result == 0) {
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VERBOSE("Using FIP\n");
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io_close(local_image_handle);
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}
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}
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return result;
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}
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#ifndef IMX8MM_FIP_MMAP
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static int open_mmc(const uintptr_t spec)
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{
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int result;
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uintptr_t local_handle;
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result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
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if (result == 0) {
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result = io_open(mmc_dev_handle, spec, &local_handle);
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if (result == 0) {
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io_close(local_handle);
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}
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}
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return result;
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}
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#else
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static int open_memmap(const uintptr_t spec)
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{
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int result;
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uintptr_t local_image_handle;
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result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
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if (result == 0) {
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result = io_open(memmap_dev_handle, spec, &local_image_handle);
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if (result == 0) {
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VERBOSE("Using Memmap\n");
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io_close(local_image_handle);
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}
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}
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return result;
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}
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#endif
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int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
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uintptr_t *image_spec)
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{
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int result;
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const struct plat_io_policy *policy;
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assert(image_id < ARRAY_SIZE(policies));
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policy = &policies[image_id];
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result = policy->check(policy->image_spec);
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assert(result == 0);
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*image_spec = policy->image_spec;
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*dev_handle = *policy->dev_handle;
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return result;
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}
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void plat_imx8mm_io_setup(void)
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{
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int result __unused;
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#ifndef IMX8MM_FIP_MMAP
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result = register_io_dev_block(&mmc_dev_con);
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assert(result == 0);
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result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
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&mmc_dev_handle);
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assert(result == 0);
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#else
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result = register_io_dev_memmap(&memmap_dev_con);
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assert(result == 0);
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result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
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&memmap_dev_handle);
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assert(result == 0);
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#endif
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result = register_io_dev_fip(&fip_dev_con);
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assert(result == 0);
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result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
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&fip_dev_handle);
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assert(result == 0);
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}
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX8MM_PRIVATE_H
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#define IMX8MM_PRIVATE_H
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/*******************************************************************************
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* Function and variable prototypes
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******************************************************************************/
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void plat_imx8mm_io_setup(void);
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#endif /* IMX8MM_PRIVATE_H */
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@ -1,9 +1,11 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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@ -34,11 +36,27 @@
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#define PLAT_SDEI_NORMAL_PRI 0x20
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#define PLAT_SDEI_SGI_PRIVATE U(9)
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#if defined(NEED_BL2)
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#define BL2_BASE U(0x920000)
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#define BL2_LIMIT U(0x940000)
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#define BL31_BASE U(0x900000)
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#define BL31_LIMIT U(0x920000)
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#define IMX8MM_FIP_BASE U(0x40310000)
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#define IMX8MM_FIP_SIZE U(0x000200000)
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#define IMX8MM_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
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/* Define FIP image location on eMMC */
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#define IMX8MM_FIP_MMC_BASE U(0x100000)
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#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */
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#else
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#define BL31_BASE U(0x920000)
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#define BL31_LIMIT U(0x940000)
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#endif
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/* non-secure uboot base */
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#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
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#define PLAT_NS_IMAGE_SIZE U(0x00100000)
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/* GICv3 base address */
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#define PLAT_GICD_BASE U(0x38800000)
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@ -127,3 +145,7 @@
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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#define IMX_WDOG_B_RESET
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#define MAX_IO_HANDLES 3U
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#define MAX_IO_DEVICES 2U
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#define MAX_IO_BLOCK_DEVICES 1U
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