Merge changes I72846d86,I70c3d873,If675796a,I0dbf8091,Ie4f3ac83, ... into integration
* changes: rcar_gen3: plat: Minor coding style fix for rcar_version.h rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6 rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: board: Add new board revision for M3ULCB rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.5 rcar_gen3: plat: Change fixed destination address of BL31 and BL32
This commit is contained in:
commit
522338b931
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
|
||||
* reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
@ -33,7 +33,7 @@
|
|||
#define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define SKP_ID { 0x10U, 0x10U, 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define SK_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define SK_ID { 0x10U, 0x30U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
#define DR_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
@ -510,6 +510,14 @@ static void send_dbcmd(uint32_t cmd)
|
|||
dsb_sev();
|
||||
}
|
||||
|
||||
static void dbwait_loop(uint32_t wait_loop)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < wait_loop; i++)
|
||||
wait_dbcmd();
|
||||
}
|
||||
|
||||
/* DDRPHY register access (raw) */
|
||||
static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
|
||||
{
|
||||
|
@ -866,6 +874,7 @@ struct _jedec_spec1 {
|
|||
uint8_t WL;
|
||||
uint8_t nwr;
|
||||
uint8_t nrtp;
|
||||
uint8_t odtlon;
|
||||
uint8_t MR1;
|
||||
uint8_t MR2;
|
||||
};
|
||||
|
@ -877,21 +886,21 @@ struct _jedec_spec1 {
|
|||
#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
|
||||
const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
|
||||
/* 533.333Mbps */
|
||||
{ 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 },
|
||||
{ 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 },
|
||||
/* 1066.666Mbps */
|
||||
{ 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 },
|
||||
{ 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 },
|
||||
/* 1600.000Mbps */
|
||||
{ 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 },
|
||||
{ 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 },
|
||||
/* 2133.333Mbps */
|
||||
{ 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) },
|
||||
{ 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) },
|
||||
/* 2666.666Mbps */
|
||||
{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },
|
||||
{ 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) },
|
||||
/* 3200.000Mbps */
|
||||
{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },
|
||||
{ 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) },
|
||||
/* 3733.333Mbps */
|
||||
{ 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) },
|
||||
{ 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) },
|
||||
/* 4266.666Mbps */
|
||||
{ 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) }
|
||||
{ 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) }
|
||||
};
|
||||
|
||||
struct _jedec_spec2 {
|
||||
|
@ -921,7 +930,8 @@ struct _jedec_spec2 {
|
|||
#define js2_tzqcalns 19
|
||||
#define js2_tzqlat 20
|
||||
#define js2_tiedly 21
|
||||
#define JS2_TBLCNT 22
|
||||
#define js2_tODTon_min 22
|
||||
#define JS2_TBLCNT 23
|
||||
|
||||
#define js2_trcpb (JS2_TBLCNT)
|
||||
#define js2_trcab (JS2_TBLCNT + 1)
|
||||
|
@ -954,7 +964,8 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
|
|||
/*tMRD*/ {14000, 10},
|
||||
/*tZQCALns*/ {1000 * 10, 0},
|
||||
/*tZQLAT*/ {30000, 10},
|
||||
/*tIEdly*/ {12500, 0}
|
||||
/*tIEdly*/ {12500, 0},
|
||||
/*tODTon_min*/ {1500, 0}
|
||||
}, {
|
||||
/*tSR */ {15000, 3},
|
||||
/*tXP */ {7500, 3},
|
||||
|
@ -977,7 +988,8 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
|
|||
/*tMRD*/ {14000, 10},
|
||||
/*tZQCALns*/ {1000 * 10, 0},
|
||||
/*tZQLAT*/ {30000, 10},
|
||||
/*tIEdly*/ {12500, 0}
|
||||
/*tIEdly*/ {12500, 0},
|
||||
/*tODTon_min*/ {1500, 0}
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -1452,7 +1464,7 @@ static void ddrtbl_load(void)
|
|||
if ((prr_product == PRR_PRODUCT_M3N) ||
|
||||
(prr_product == PRR_PRODUCT_V3H)) {
|
||||
ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
|
||||
_reg_PHY_RDDATA_EN_OE_DLY, dataS);
|
||||
_reg_PHY_RDDATA_EN_OE_DLY, dataS - 2);
|
||||
}
|
||||
ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
|
||||
|
||||
|
@ -1501,6 +1513,7 @@ static void ddrtbl_load(void)
|
|||
/* non */
|
||||
} else {
|
||||
regif_pll_wa();
|
||||
dbwait_loop(5);
|
||||
}
|
||||
|
||||
/* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
|
||||
|
@ -2067,12 +2080,18 @@ static void dbsc_regset(void)
|
|||
/* DBTR9.TRDPR : tRTP */
|
||||
mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
|
||||
|
||||
/* DBTR10.TWR : nwr */
|
||||
/* DBTR10.TWR : nWR */
|
||||
mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
|
||||
|
||||
/* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
|
||||
/*
|
||||
* DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
|
||||
* odtlon + tDQSCK - tODTon,min +
|
||||
* PCB delay (out+in) + tPHY_ODToff
|
||||
*/
|
||||
mmio_write_32(DBSC_DBTR(11),
|
||||
RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2);
|
||||
RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon +
|
||||
js2[js2_tdqsck] - js2[js2_tODTon_min] +
|
||||
_f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
|
||||
|
||||
/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
|
||||
data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
|
||||
|
@ -2338,10 +2357,23 @@ static void dbsc_regset_post(void)
|
|||
}
|
||||
}
|
||||
if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
|
||||
#if RCAR_DRAM_SPLIT == 2
|
||||
if (board_cnf->phyvalid == 0x05) {
|
||||
mmio_write_32(DBSC_DBTR(24),
|
||||
(rdlat_max << 24) + (rdlat_min << 16) +
|
||||
mmio_read_32(DBSC_DBTR(24)));
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBTR(24),
|
||||
((rdlat_max * 2 - rdlat_min + 4) << 24) +
|
||||
((rdlat_min + 2) << 16) +
|
||||
mmio_read_32(DBSC_DBTR(24)));
|
||||
}
|
||||
#else /*RCAR_DRAM_SPLIT == 2 */
|
||||
mmio_write_32(DBSC_DBTR(24),
|
||||
((rdlat_max * 2 - rdlat_min + 4) << 24) +
|
||||
((rdlat_min + 2) << 16) +
|
||||
mmio_read_32(DBSC_DBTR(24)));
|
||||
#endif /*RCAR_DRAM_SPLIT == 2 */
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBTR(24),
|
||||
((rdlat_max + 2) << 24) +
|
||||
|
@ -2383,37 +2415,6 @@ static void dbsc_regset_post(void)
|
|||
mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
|
||||
mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
|
||||
|
||||
#ifdef DDR_BACKUPMODE
|
||||
if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
|
||||
#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
|
||||
DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
|
||||
send_dbcmd(0x08040001);
|
||||
wait_dbcmd();
|
||||
send_dbcmd(0x0A040001);
|
||||
wait_dbcmd();
|
||||
send_dbcmd(0x04040010);
|
||||
wait_dbcmd();
|
||||
|
||||
if (prr_product == PRR_PRODUCT_H3) {
|
||||
send_dbcmd(0x08140001);
|
||||
wait_dbcmd();
|
||||
send_dbcmd(0x0A140001);
|
||||
wait_dbcmd();
|
||||
send_dbcmd(0x04140010);
|
||||
wait_dbcmd();
|
||||
}
|
||||
#else /* DDR_BACKUPMODE_HALF //for All channels */
|
||||
send_dbcmd(0x08840001);
|
||||
wait_dbcmd();
|
||||
send_dbcmd(0x0A840001);
|
||||
wait_dbcmd();
|
||||
|
||||
send_dbcmd(0x04840010);
|
||||
wait_dbcmd();
|
||||
#endif /* DDR_BACKUPMODE_HALF */
|
||||
}
|
||||
#endif /* DDR_BACKUPMODE */
|
||||
|
||||
#if RCAR_REWT_TRAINING != 0
|
||||
/* Periodic-WriteDQ Training seeting */
|
||||
if (((prr_product == PRR_PRODUCT_H3) &&
|
||||
|
@ -2422,12 +2423,7 @@ static void dbsc_regset_post(void)
|
|||
(prr_cut == PRR_PRODUCT_10))) {
|
||||
/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
|
||||
} else {
|
||||
/*
|
||||
* H3 Ver.2.0 or later/M3-W Ver.1.1 or
|
||||
* later/M3-N/V3H -> Periodic-WriteDQ Training seeting
|
||||
*/
|
||||
|
||||
/* Periodic WriteDQ Training seeting */
|
||||
/* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
|
||||
mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
|
||||
|
||||
ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
|
||||
|
@ -2440,7 +2436,6 @@ static void dbsc_regset_post(void)
|
|||
_reg_PI_WDQLVL_CS_MAP));
|
||||
ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
|
||||
ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
|
||||
ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
|
||||
ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
|
||||
ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
|
||||
ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
|
||||
|
@ -2458,8 +2453,10 @@ static void dbsc_regset_post(void)
|
|||
mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING */
|
||||
/* periodic dram zqcal and phy ctrl update enable */
|
||||
/* periodic dram zqcal enable */
|
||||
mmio_write_32(DBSC_DBCALCNF, 0x01000010);
|
||||
|
||||
/* periodic phy ctrl update enable */
|
||||
if (((prr_product == PRR_PRODUCT_H3) &&
|
||||
(prr_cut <= PRR_PRODUCT_11)) ||
|
||||
((prr_product == PRR_PRODUCT_M3) &&
|
||||
|
@ -2477,7 +2474,36 @@ static void dbsc_regset_post(void)
|
|||
#endif /* RCAR_DRAM_SPLIT == 2 */
|
||||
}
|
||||
|
||||
#ifdef DDR_BACKUPMODE
|
||||
/* SRX */
|
||||
if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
|
||||
#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
|
||||
NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
|
||||
send_dbcmd(0x0A040001);
|
||||
if (Prr_Product == PRR_PRODUCT_H3)
|
||||
send_dbcmd(0x0A140001);
|
||||
#else /* DDR_BACKUPMODE_HALF */ /* for All channels */
|
||||
send_dbcmd(0x0A840001);
|
||||
#endif /* DDR_BACKUPMODE_HALF */
|
||||
}
|
||||
#endif /* DDR_BACKUPMODE */
|
||||
|
||||
/* set Auto Refresh */
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
|
||||
#if RCAR_REWT_TRAINING != 0
|
||||
/* Periodic WriteDQ Traning */
|
||||
if (((prr_product == PRR_PRODUCT_H3) &&
|
||||
(prr_cut <= PRR_PRODUCT_11)) ||
|
||||
((prr_product == PRR_PRODUCT_M3) &&
|
||||
(prr_cut == PRR_PRODUCT_10))) {
|
||||
/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
|
||||
} else {
|
||||
/* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
|
||||
ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
|
||||
}
|
||||
#endif /* RCAR_REWT_TRAINING */
|
||||
|
||||
/* dram access enable */
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
|
||||
|
@ -3026,6 +3052,9 @@ static uint32_t init_ddr(void)
|
|||
return INITDRAM_ERR_O;
|
||||
MSG_LF(__func__ ":5\n");
|
||||
|
||||
/* Dummy PDE */
|
||||
send_dbcmd(0x08840000);
|
||||
|
||||
/* PDX */
|
||||
send_dbcmd(0x08840001);
|
||||
|
||||
|
@ -3477,10 +3506,13 @@ static uint32_t wdqdm_man(void)
|
|||
{
|
||||
uint32_t err, retry_cnt;
|
||||
const uint32_t retry_max = 0x10;
|
||||
uint32_t ch, ddr_csn, mr14_bkup[4][4];
|
||||
uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
|
||||
|
||||
datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19;
|
||||
if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal)
|
||||
datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
|
||||
ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
|
||||
|
||||
ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW,
|
||||
(mmio_read_32(DBSC_DBTR(11)) & 0xFF) + 19);
|
||||
if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
|
||||
(prr_product == PRR_PRODUCT_M3N) ||
|
||||
(prr_product == PRR_PRODUCT_V3H)) {
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
@ -1571,8 +1571,13 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
|
|||
{
|
||||
uint32_t md;
|
||||
|
||||
if (prr_product == PRR_PRODUCT_V3H) {
|
||||
md = (mmio_read_32(RST_MODEMR) >> 19) & 0x1;
|
||||
md = (md | (md << 1)) & 0x3; /* 0 or 3 */
|
||||
} else {
|
||||
md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
|
||||
md = (md | (md >> 1)) & 0x3;
|
||||
}
|
||||
switch (md) {
|
||||
case 0x0:
|
||||
*mbps = 3200;
|
||||
|
@ -1722,8 +1727,13 @@ static uint32_t _board_judge(void)
|
|||
#endif
|
||||
}
|
||||
} else if (prr_product == PRR_PRODUCT_M3) {
|
||||
if (prr_cut >= PRR_PRODUCT_30) {
|
||||
/* RENESAS Starter Kit (M3-W Ver.3.0/SIP) */
|
||||
brd = 18;
|
||||
} else {
|
||||
/* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
|
||||
brd = 3;
|
||||
}
|
||||
} else {
|
||||
/* RENESAS Starter Kit(M3-N/SIP) board */
|
||||
brd = 11;
|
||||
|
|
|
@ -1,11 +1,11 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define RCAR_DDR_VERSION "rev.0.37"
|
||||
#define RCAR_DDR_VERSION "rev.0.40"
|
||||
#define DRAM_CH_CNT 0x04
|
||||
#define SLICE_CNT 0x04
|
||||
#define CS_CNT 0x02
|
||||
|
@ -22,7 +22,7 @@
|
|||
|
||||
/* for ddr deisity setting */
|
||||
#define DBMEMCONF_REG(d3, row, bank, col, dw) \
|
||||
((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
|
||||
(((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
|
||||
|
||||
#define DBMEMCONF_REGD(density) \
|
||||
(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
|
@ -116,7 +116,7 @@ static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
|
|||
/*0859*/ 0x00000200,
|
||||
/*085a*/ 0x00000004,
|
||||
/*085b*/ 0x4041a151,
|
||||
/*085c*/ 0x0141c0a0,
|
||||
/*085c*/ 0x0141a0a0,
|
||||
/*085d*/ 0x0000c0c0,
|
||||
/*085e*/ 0x0e0c000e,
|
||||
/*085f*/ 0x10001000,
|
||||
|
|
|
@ -16,6 +16,8 @@
|
|||
#include <common/debug.h>
|
||||
#include <common/desc_image_load.h>
|
||||
#include <drivers/console.h>
|
||||
#include <drivers/io/io_driver.h>
|
||||
#include <drivers/io/io_storage.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_defs.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
@ -33,6 +35,7 @@
|
|||
#endif
|
||||
|
||||
#include "io_common.h"
|
||||
#include "io_rcar.h"
|
||||
#include "qos_init.h"
|
||||
#include "rcar_def.h"
|
||||
#include "rcar_private.h"
|
||||
|
@ -382,10 +385,28 @@ cold_boot:
|
|||
return 0;
|
||||
}
|
||||
|
||||
static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest)
|
||||
{
|
||||
uint32_t cert, len;
|
||||
int ret;
|
||||
|
||||
ret = rcar_get_certificate(certid, &cert);
|
||||
if (ret) {
|
||||
ERROR("%s : cert file load error", __func__);
|
||||
return 1;
|
||||
}
|
||||
|
||||
rcar_read_certificate((uint64_t) cert, &len, dest);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
static bl2_to_bl31_params_mem_t *params;
|
||||
bl_mem_params_node_t *bl_mem_params;
|
||||
uintptr_t dest;
|
||||
int ret;
|
||||
|
||||
if (!params) {
|
||||
params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
|
||||
|
@ -396,8 +417,17 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
|
|||
|
||||
switch (image_id) {
|
||||
case BL31_IMAGE_ID:
|
||||
ret = rcar_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID,
|
||||
&dest);
|
||||
if (!ret)
|
||||
bl_mem_params->image_info.image_base = dest;
|
||||
break;
|
||||
case BL32_IMAGE_ID:
|
||||
ret = rcar_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID,
|
||||
&dest);
|
||||
if (!ret)
|
||||
bl_mem_params->image_info.image_base = dest;
|
||||
|
||||
memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
|
||||
sizeof(entry_point_info_t));
|
||||
break;
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
|
||||
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -9,8 +9,8 @@
|
|||
|
||||
#include <arch_helpers.h>
|
||||
|
||||
#define VERSION_OF_RENESAS "2.0.4"
|
||||
#define VERSION_OF_RENESAS_MAXLEN (128)
|
||||
#define VERSION_OF_RENESAS "2.0.6"
|
||||
#define VERSION_OF_RENESAS_MAXLEN 128
|
||||
|
||||
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
|
||||
|
||||
|
|
Loading…
Reference in New Issue