feat(docs/nxp/layerscape): add ls1028a soc and board support
Update nxp-layerscape to add ls1028a SoC and ls1028ardb board support. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I9c7cc586f3718b488a6757994d65f6df69e7e165
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@ -5,22 +5,62 @@ NXP SoCs - Overview
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The QorIQ family of ARM based SoCs that are supported on TF-A are:
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1. LX2160ARDB:
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Platform Name:
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1. LX2160A
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a. lx2160ardb (Board details can be fetched from the link: `lx2160ardb`_)
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- SoC Overview:
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The LX2160A multicore processor, the highest-performance member of the
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Layerscape family, combines FinFET process technology's low power and
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sixteen Arm® Cortex®-A72 cores with datapath acceleration optimized for
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L2/3 packet processing, together with security offload, robust traffic
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management and quality of service.
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Details about LX2160A can be found at `lx2160a`_.
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- LX2160ARDB Board:
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The LX2160A reference design board provides a comprehensive platform
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that enables design and evaluation of the LX2160A or LX2162A processors. It
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comes preloaded with a board support package (BSP) based on a standard Linux
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kernel.
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Board details can be fetched from the link: `lx2160ardb`_.
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2. LS1028A
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- SoC Overview:
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The Layerscape LS1028A applications processor for industrial and
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automotive includes a time-sensitive networking (TSN) -enabled Ethernet
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switch and Ethernet controllers to support converged IT and OT networks.
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Two powerful 64-bit Arm®v8 cores support real-time processing for
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industrial control and virtual machines for edge computing in the IoT.
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The integrated GPU and LCD controller enable Human-Machine Interface
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(HMI) systems with next-generation interfaces.
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Details about LS1028A can be found at `ls1028a`_.
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- LS1028ARDB Boards:
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The LS1028A reference design board (RDB) is a computing, evaluation,
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and development platform that supports industrial IoT applications, human
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machine interface solutions, and industrial networking.
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Details about LS1028A RDB board can be found at `ls1028ardb`_.
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Table of supported boot-modes by each platform & platform that needs FIP-DDR:
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-----------------------------------------------------------------------------
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+---+-----------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| | BOOT_MODE-->| sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | fip_ddr needed |
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| | | | | | | | | | |
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| | PLAT | | | | | | | | |
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+===+=================+=======+========+=======+=======+=======+=============+==============+=================+
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| 1.| lx2160ardb | yes | | | | yes | yes | | yes |
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+---+-----------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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+---------------------+---------------------------------------------------------------------+-----------------+
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| | BOOT_MODE | |
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| PLAT +-------+--------+-------+-------+-------+-------------+--------------+ fip_ddr_needed |
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| | sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | |
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+=====================+=======+========+=======+=======+=======+=============+==============+=================+
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| lx2160ardb | yes | | | | yes | yes | | yes |
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| ls1028ardb | yes | | | | yes | yes | | no |
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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Boot Sequence
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-------------
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@ -54,6 +94,32 @@ Boot Sequence with FIP-DDR
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+ EL3 BootROM --> BL2 -----> BL31 ---------------/
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+
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DDR Memory Layout
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--------------------------
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NXP Platforms divide DRAM into banks:
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- DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h if it is less than 2GB.
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- DRAM1 ~ DRAMn Bank: Greater than 2GB belongs to DRAM1 and following banks, and size of DRAMn Bank varies for one platform to others.
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The following diagram is default DRAM0 memory layout in which secure memory is at top of DRAM0.
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::
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high +---------------------------------------------+
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| Secure EL1 Payload Shared Memory (2 MB) |
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+---------------------------------------------+
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| Secure Memory (64 MB) |
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+---------------------------------------------+
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| Non Secure Memory |
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low +---------------------------------------------+
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How to build
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=============
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@ -228,5 +294,8 @@ For TBBR, the binary name changes:
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Refer `nxp-ls-tbbr.rst`_ for detailed user steps.
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.. _lx2160a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A
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.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A
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.. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A
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.. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB
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.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
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