plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
This commit is contained in:
Oliver Swede
parent
c979685271
commit
536d906abc
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <platform_def.h>
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl platform_mem_init
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.globl plat_my_core_pos
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.globl plat_fpga_calc_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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/* -----------------------------------------------------------------------
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* unsigned long plat_get_my_entrypoint (void);
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* TODO: determine if warm boot should be supported for FPGA images
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* -----------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov x0, #0
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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* TODO: add placeholder PSCI implementation for FPGA images
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* -----------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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ret
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary cpu
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* -----------------------------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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mov_imm x1, MPIDR_AFFINITY_MASK
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and x0, x0, x1
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cmp x0, #FPGA_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_fpga_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------------------------
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* unsigned int plat_fpga_calc_core_pos(u_register_t mpidr)
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* TODO: add calculation of the core position for FPGA image CPUs
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* -----------------------------------------------------------------------
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*/
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func plat_fpga_calc_core_pos
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mov x0, #0
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ret
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endfunc plat_fpga_calc_core_pos
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func plat_crash_console_init
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mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
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mov_imm x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ
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mov_imm x2, PLAT_FPGA_CONSOLE_BAUDRATE
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b console_pl011_core_init
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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mov_imm x1, PLAT_FPGA_CRASH_UART_BASE
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b console_pl011_core_putc
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
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b console_pl011_core_flush
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endfunc plat_crash_console_flush
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "fpga_private.h"
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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fpga_console_init();
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/*
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* TODO: implement any extra early platform setup before jumping to BL33
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* payload
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*/
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}
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void bl31_plat_arch_setup(void)
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{
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}
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void bl31_platform_setup(void)
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{
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/* TODO: initialize GIC and timer using the specifications of the FPGA image */
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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/*
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* TODO: return entry_point_info_t struct containing information about the
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* BL33 payload, which will run in EL2NS mode.
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*/
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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/*
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* TODO: return the frequency of the System Counter as configured by the
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* FPGA image
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*/
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return 0;
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}
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void bl31_plat_enable_mmu(uint32_t flags)
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{
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/* TODO: determine if MMU needs to be enabled */
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/console.h>
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#include <drivers/arm/pl011.h>
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#include <platform_def.h>
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static console_t console;
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void fpga_console_init(void)
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{
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(void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE,
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PLAT_FPGA_BOOT_UART_CLK_IN_HZ,
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PLAT_FPGA_CONSOLE_BAUDRATE,
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&console);
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console_set_scope(&console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME);
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/utils_def.h>
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#ifndef FPGA_DEF_H
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#define FPGA_DEF_H
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/*
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* The initial FPGA image configures a system with 2 clusters, 1 core in each,
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* and multi-threading is unimplemented.
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*/
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#define FPGA_MAX_CLUSTER_COUNT 2
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#define FPGA_MAX_CPUS_PER_CLUSTER 1
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#define FPGA_MAX_PE_PER_CPU 1
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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/* UART base address and clock frequency, as configured by the image */
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#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
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#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000
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#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
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#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
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#endif
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/common/platform.h>
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/* TODO: add PSCI implementation */
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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return 0;
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FPGA_PRIVATE_H
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#define FPGA_PRIVATE_H
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unsigned int plat_fpga_calc_core_pos(u_register_t mpidr);
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void fpga_console_init(void);
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#endif
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include "fpga_private.h"
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#include <platform_def.h>
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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/* TODO: add description of power domain topology and PSCI implementation */
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return NULL;
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}
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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/*
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* TODO: calculate core position in a way that accounts for CPUs that
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* potentially implement multithreading
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*/
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return (int) plat_fpga_calc_core_pos(mpidr);
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}
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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.macro plat_crash_print_regs
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.endm
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#endif
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include "../fpga_def.h"
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define PLATFORM_STACK_SIZE UL(0x800)
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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#define PLATFORM_CORE_COUNT \
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(FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU)
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#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT) + 1
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#define BL31_BASE UL(0x80000000)
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#define BL31_LIMIT UL(0x80100000)
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_FPGA_CONSOLE_BAUDRATE 38400
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#endif
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#
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# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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RESET_TO_BL31 := 1
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ifeq (${RESET_TO_BL31}, 0)
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$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
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endif
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CTX_INCLUDE_AARCH32_REGS := 0
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ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
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$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
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endif
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ifeq (${TRUSTED_BOARD_BOOT}, 1)
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$(error "TRUSTED_BOARD_BOOT must be disabled")
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endif
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ifndef PRELOADED_BL33_BASE
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$(error "PRELOADED_BL33_BASE is not set")
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endif
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ifndef FPGA_PRELOADED_DTB_BASE
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$(error "FPGA_PRELOADED_DTB_BASE is not set")
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else
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$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
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endif
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# Treating this as a memory-constrained port for now
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USE_COHERENT_MEM := 0
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# The CPU in the initial image makes use of this feature
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HW_ASSISTED_COHERENCY := 1
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FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S \
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lib/cpus/aarch64/neoverse_zeus.S
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FPGA_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v3/gicv3_main.c \
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plat/common/plat_gicv3.c
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PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
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BL31_SOURCES += drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/arm/pl011/${ARCH}/pl011_console.S \
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plat/common/plat_psci_common.c \
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plat/arm/board/arm_fpga/fpga_pm.c \
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plat/arm/board/arm_fpga/fpga_topology.c \
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plat/arm/board/arm_fpga/fpga_console.c \
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plat/arm/board/arm_fpga/fpga_bl31_setup.c \
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${FPGA_CPU_LIBS} \
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${FPGA_GIC_SOURCES}
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all: bl31
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