rcar_gen3: plat: Fix cache line size
The CPU has cache line size of 64 Bytes, fix the cache line size. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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@ -79,7 +79,7 @@
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* Cortex-A53
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* Cortex-A53
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* L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
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* L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
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*/
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*/
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#define PLATFORM_CACHE_LINE_SIZE 128
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
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