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synquacer: Enable System level Generic timer 

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg 2018-06-15 15:02:31 +05:30
parent b529799ff1
commit 5931fdac63
2 changed files with 41 additions and 0 deletions
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5
plat/socionext/synquacer/include/platform_def.h
View File

@ -44,6 +44,11 @@
#define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000
#define SQ_CONSOLE_BAUDRATE 115200
#define SQ_SYS_CNTCTL_BASE 0x2a430000
#define SQ_SYS_TIMCTL_BASE 0x2a810000
#define PLAT_SQ_NSTIMER_FRAME_ID 0
#define SQ_BOOT_CFG_ADDR 0x45410000
#define PLAT_SQ_PRIMARY_CPU_SHIFT 8
#define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6

36
plat/socionext/synquacer/sq_bl31_setup.c
View File

@ -11,6 +11,7 @@
#include <bl_common.h>
#include <pl011.h>
#include <debug.h>
#include <mmio.h>
#include <sq_common.h>
static console_pl011_t console;
@ -94,6 +95,20 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
static void sq_configure_sys_timer(void)
{
unsigned int reg_val;
reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
mmio_write_32(SQ_SYS_TIMCTL_BASE +
CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val);
reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID));
mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
}
void bl31_platform_setup(void)
{
/* Initialize the CCN interconnect */
@ -103,6 +118,13 @@ void bl31_platform_setup(void)
/* Initialize the GIC driver, cpu and distributor interfaces */
sq_gic_driver_init();
sq_gic_init();
/* Enable and initialize the System level generic timer */
mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
/* Allow access to the System counter timer module */
sq_configure_sys_timer();
}
void bl31_plat_runtime_setup(void)
@ -112,3 +134,17 @@ void bl31_plat_runtime_setup(void)
void bl31_plat_arch_setup(void)
{
}
unsigned int plat_get_syscnt_freq2(void)
{
unsigned int counter_base_frequency;
/* Read the frequency from Frequency modes table */
counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF);
/* The first entry of the frequency modes table must not be 0 */
if (counter_base_frequency == 0)
panic();
return counter_base_frequency;
}