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Merge pull request #1511 from chandnich/sgi575-updates 

Sgi575 updates
This commit is contained in:
Dimitris Papastamos 2018-08-03 14:16:31 +01:00 committed by GitHub
parent f68bc8a1c2 a41d1b2ce3
commit 60e27d5644
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 51 additions and 25 deletions
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60
plat/arm/css/sgi/aarch64/sgi_helper.S
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@ -7,28 +7,10 @@
#include <arch.h>
#include <asm_macros.S>
#include <platform_def.h>
#include <cortex_a75.h>
.globl plat_is_my_cpu_primary
.globl plat_arm_calc_core_pos
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current cpu is the primary
* cpu (applicable only after a cold boot)
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
mov x9, x30
bl plat_my_core_pos
ldr x1, =SGI_BOOT_CFG_ADDR
ldr x1, [x1]
ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
cmp x0, x1
cset w0, eq
ret x9
endfunc plat_is_my_cpu_primary
.globl plat_reset_handler
/* -----------------------------------------------------
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
@ -65,3 +47,41 @@ func plat_arm_calc_core_pos
madd x0, x1, x5, x0
ret
endfunc plat_arm_calc_core_pos
/* ------------------------------------------------------
* Helper macro that reads the part number of the current
* CPU and jumps to the given label if it matches the CPU
* MIDR provided.
*
* Clobbers x0.
* -----------------------------------------------------
*/
.macro jump_if_cpu_midr _cpu_midr, _label
mrs x0, midr_el1
ubfx x0, x0, MIDR_PN_SHIFT, #12
cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
b.eq \_label
.endm
/* -----------------------------------------------------
* void plat_reset_handler(void);
*
* Determine the CPU MIDR and disable power down bit for
* that CPU.
* -----------------------------------------------------
*/
func plat_reset_handler
jump_if_cpu_midr CORTEX_A75_MIDR, A75
ret
/* -----------------------------------------------------
* Disable CPU power down bit in power control register
* -----------------------------------------------------
*/
A75:
mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
msr CORTEX_A75_CPUPWRCTLR_EL1, x0
isb
ret
endfunc plat_reset_handler

5
plat/arm/css/sgi/include/platform_def.h
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@ -77,11 +77,6 @@
CSS_SGI_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
#define SGI_BOOT_CFG_ADDR 0x45410000
#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6
/* GIC related constants */
#define PLAT_ARM_GICD_BASE 0x30000000
#define PLAT_ARM_GICC_BASE 0x2C000000

2
plat/arm/css/sgi/sgi-common.mk
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@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
CSS_USE_SCMI_SDS_DRIVER := 1
ENABLE_PLAT_COMPAT := 0
CSS_ENT_BASE := plat/arm/css/sgi

9
plat/arm/css/sgi/sgi_topology.c
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@ -42,3 +42,12 @@ unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
{
return sgi_topology.plat_cluster_core_count;
}
/*******************************************************************************
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
};