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drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64() 

ESPI register offset should also be shifted right by REG##R_SHIFT to
keep consistent.

It is not a functional issue, for GICD_OFFSET_64() is only used for
GICD_IROUTER<E>, and IROUTER_SHIFT is 0.

Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com>
Change-Id: I76eee5c50e4300890e78e80bddde135ce88daa2d
This commit is contained in:
Heyi Guo 2020-05-19 16:45:17 +08:00 committed by Manish Pandey
parent 705032deea
commit 612b4a3f2d
1 changed files with 3 additions and 2 deletions
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5
drivers/arm/gic/v3/gicv3_private.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,7 +48,8 @@
#define GICD_OFFSET_64(REG, id) \
(((id) <= MAX_SPI_ID) ? \
GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3))
GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
REG##R_SHIFT) << 3))
#else /* GICv3 */
#define GICD_OFFSET_8(REG, id) \