qemu/qemu_sbsa: enable SPM support
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
This commit is contained in:
Masahisa Kojima
Manish Pandey
parent
3ee8e4d8de
commit
6a2426a94f
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@ -19,7 +19,6 @@ and also enable methods for the CPUs.
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Current limitations:
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- Only cold boot is supported
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- No instructions for how to load a BL32 (Secure Payload)
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To build TF-A:
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@ -27,9 +26,18 @@ To build TF-A:
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git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
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cd tfa
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export CROSS_COMPILE=aarch64-linux-gnu-
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export CROSS_COMPILE=aarch64-none-elf-
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make PLAT=qemu_sbsa all fip
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To build TF-A with BL32 and SPM enabled(StandaloneMM as a Secure Payload):
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::
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git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git tfa
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cd tfa
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export CROSS_COMPILE=aarch64-none-elf-
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make PLAT=qemu_sbsa BL32=../STANDALONE_MM.fd SPM_MM=1 EL3_EXCEPTION_HANDLING=1 all fip
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Images will be placed at build/qemu_sbsa/release (bl1.bin and fip.bin).
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Need to copy them into top directory for EDK2 compilation.
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -77,7 +78,11 @@ static const mmap_region_t plat_qemu_mmap[] = {
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MAP_DEVICE2,
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#endif
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MAP_NS_DRAM0,
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#if SPM_MM
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QEMU_SP_IMAGE_MMAP,
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#else
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MAP_BL32_MEM,
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#endif
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{0}
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};
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#endif
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@ -88,7 +93,11 @@ static const mmap_region_t plat_qemu_mmap[] = {
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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#if SPM_MM
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QEMU_SPM_BUF_EL3_MMAP,
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#else
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MAP_BL32_MEM,
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#endif
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{0}
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};
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#endif
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@ -0,0 +1,81 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2020, Linaro Limited and Contributors. All rights reserved.
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*/
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#include <bl31/ehf.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <services/spm_mm_partition.h>
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#include <platform_def.h>
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/* Region equivalent to MAP_DEVICE1 suitable for mapping at EL0 */
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#define MAP_DEVICE1_EL0 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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const mmap_region_t plat_qemu_secure_partition_mmap[] = {
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MAP_DEVICE1_EL0, /* for the UART */
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QEMU_SP_IMAGE_MMAP,
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QEMU_SPM_BUF_EL0_MMAP,
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QEMU_SP_IMAGE_NS_BUF_MMAP,
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QEMU_SP_IMAGE_RW_MMAP,
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{0}
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};
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/*
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* Boot information passed to a secure partition during initialisation.
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* Linear indices in MP information will be filled at runtime.
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*/
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static spm_mm_mp_info_t sp_mp_info[] = {
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[0] = {0x80000000, 0},
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[1] = {0x80000001, 0},
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[2] = {0x80000002, 0},
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[3] = {0x80000003, 0},
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[4] = {0x80000004, 0},
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[5] = {0x80000005, 0},
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[6] = {0x80000006, 0},
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[7] = {0x80000007, 0}
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};
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const spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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.h.version = VERSION_1,
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.h.size = sizeof(spm_mm_boot_info_t),
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.h.attr = 0,
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.sp_mem_base = PLAT_QEMU_SP_IMAGE_BASE,
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.sp_mem_limit = BL32_LIMIT,
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.sp_image_base = PLAT_QEMU_SP_IMAGE_BASE,
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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.sp_heap_base = PLAT_QEMU_SP_IMAGE_HEAP_BASE,
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.sp_ns_comm_buf_base = PLAT_QEMU_SP_IMAGE_NS_BUF_BASE,
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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.sp_image_size = PLAT_QEMU_SP_IMAGE_SIZE,
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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.sp_heap_size = PLAT_QEMU_SP_IMAGE_HEAP_SIZE,
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.sp_ns_comm_buf_size = PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE,
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
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.num_sp_mem_regions = PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS,
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.num_cpus = PLATFORM_CORE_COUNT,
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.mp_info = sp_mp_info
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};
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/* Enumeration of priority levels on QEMU platforms. */
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ehf_pri_desc_t qemu_exceptions[] = {
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EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI)
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};
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/* Plug in QEMU exceptions to Exception Handling Framework. */
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EHF_REGISTER_PRIORITIES(qemu_exceptions, ARRAY_SIZE(qemu_exceptions),
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QEMU_PRI_BITS);
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const mmap_region_t *plat_get_secure_partition_mmap(void *cookie)
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{
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return plat_qemu_secure_partition_mmap;
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}
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const spm_mm_boot_info_t *
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plat_get_secure_partition_boot_info(void *cookie)
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{
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return &plat_qemu_secure_partition_boot_info;
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}
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@ -1,10 +1,11 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Linaro Limited and Contributors.
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* All rights reserved.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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@ -107,9 +108,10 @@
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* Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using
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* the current BL1 RW debug size plus a little space for growth.
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*/
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#define BL1_SIZE 0x12000
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#define BL1_RO_BASE SEC_ROM_BASE
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#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE)
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#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000)
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#define BL1_RW_BASE (BL1_RW_LIMIT - BL1_SIZE)
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#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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/*
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@ -118,7 +120,8 @@
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* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
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* size plus a little space for growth.
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*/
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#define BL2_BASE (BL31_BASE - 0x1D000)
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#define BL2_SIZE 0x1D000
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#define BL2_BASE (BL31_BASE - BL2_SIZE)
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#define BL2_LIMIT BL31_BASE
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/*
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@ -127,8 +130,9 @@
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* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL3-1 debug size plus a little space for growth.
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*/
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#define BL31_BASE (BL31_LIMIT - 0x20000)
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#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE)
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#define BL31_SIZE 0x50000
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#define BL31_BASE (BL31_LIMIT - BL31_SIZE)
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#define BL31_LIMIT (BL1_RW_BASE)
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#define BL31_PROGBITS_LIMIT BL1_RW_BASE
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@ -138,12 +142,11 @@
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* BL3-2 can execute from Secure SRAM, or Secure DRAM.
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*/
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#define BL32_SRAM_BASE BL_RAM_BASE
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#define BL32_SRAM_LIMIT BL31_BASE
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#define BL32_DRAM_BASE SEC_DRAM_BASE
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#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
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#define BL32_SRAM_LIMIT BL2_BASE
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#define BL32_MEM_BASE BL_RAM_BASE
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#define BL32_MEM_SIZE BL_RAM_SIZE
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#define BL32_MEM_SIZE (BL_RAM_SIZE - BL1_SIZE - \
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BL2_SIZE - BL31_SIZE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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@ -152,11 +155,21 @@
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 42)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 42)
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#if SPM_MM
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#define MAX_MMAP_REGIONS 12
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#define MAX_XLAT_TABLES 11
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#else
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#define MAX_MMAP_REGIONS 11
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#define MAX_XLAT_TABLES 10
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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#if SPM_MM && defined(IMAGE_BL31)
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# define PLAT_SP_IMAGE_MMAP_REGIONS 30
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
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#endif
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/*
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* PL011 related constants
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*/
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@ -165,6 +178,10 @@
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#define UART0_CLK_IN_HZ 1
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#define UART1_CLK_IN_HZ 1
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/* Secure UART */
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#define UART2_BASE 0x60040000
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#define UART2_CLK_IN_HZ 1
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#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
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#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ
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@ -179,7 +196,7 @@
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#define QEMU_FLASH1_SIZE 0x10000000
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#define PLAT_QEMU_FIP_BASE 0x00008000
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#define PLAT_QEMU_FIP_MAX_SIZE 0x00020000
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#define PLAT_QEMU_FIP_MAX_SIZE 0x00400000
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/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */
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#define DEVICE0_BASE 0x40000000
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@ -240,4 +257,99 @@
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16)
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#endif /* __PLATFORM_DEF_H__ */
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#if SPM_MM
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#define PLAT_QEMU_SP_IMAGE_BASE BL_RAM_BASE
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#define PLAT_QEMU_SP_IMAGE_SIZE ULL(0x300000)
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#ifdef IMAGE_BL2
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/* In BL2 all memory allocated to the SPM Payload image is marked as RW. */
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# define QEMU_SP_IMAGE_MMAP MAP_REGION_FLAT( \
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PLAT_QEMU_SP_IMAGE_BASE, \
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PLAT_QEMU_SP_IMAGE_SIZE, \
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MT_MEMORY | MT_RW | \
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MT_SECURE)
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#elif IMAGE_BL31
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/* All SPM Payload memory is marked as code in S-EL0 */
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# define QEMU_SP_IMAGE_MMAP MAP_REGION2(PLAT_QEMU_SP_IMAGE_BASE, \
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PLAT_QEMU_SP_IMAGE_BASE, \
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PLAT_QEMU_SP_IMAGE_SIZE, \
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MT_CODE | MT_SECURE | \
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MT_USER, \
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PAGE_SIZE)
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#endif
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/*
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* EL3 -> S-EL0 secure shared memory
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*/
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#define PLAT_SPM_BUF_PCPU_SIZE ULL(0x10000)
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#define PLAT_SPM_BUF_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_SPM_BUF_PCPU_SIZE)
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#define PLAT_SPM_BUF_BASE (BL32_LIMIT - PLAT_SPM_BUF_SIZE)
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#define QEMU_SPM_BUF_EL3_MMAP MAP_REGION_FLAT(PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RW_DATA | MT_SECURE)
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#define QEMU_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RO_DATA | MT_SECURE | \
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MT_USER, \
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PAGE_SIZE)
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/*
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* Shared memory between Normal world and S-EL0 for
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* passing data during service requests. It will be marked as RW and NS.
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*/
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#define PLAT_QEMU_SP_IMAGE_NS_BUF_BASE (PLAT_QEMU_DT_BASE + \
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PLAT_QEMU_DT_MAX_SIZE)
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#define PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
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#define QEMU_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
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PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \
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PLAT_QEMU_SP_IMAGE_NS_BUF_BASE, \
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PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE, \
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MT_RW_DATA | MT_NS | \
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MT_USER, \
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PAGE_SIZE)
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#define PLAT_SP_IMAGE_NS_BUF_BASE PLAT_QEMU_SP_IMAGE_NS_BUF_BASE
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#define PLAT_SP_IMAGE_NS_BUF_SIZE PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE
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#define PLAT_QEMU_SP_IMAGE_HEAP_BASE (PLAT_QEMU_SP_IMAGE_BASE + \
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PLAT_QEMU_SP_IMAGE_SIZE)
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#define PLAT_QEMU_SP_IMAGE_HEAP_SIZE ULL(0x800000)
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#define PLAT_SP_IMAGE_STACK_BASE (PLAT_QEMU_SP_IMAGE_HEAP_BASE + \
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PLAT_QEMU_SP_IMAGE_HEAP_SIZE)
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000)
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#define QEMU_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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#define QEMU_SP_IMAGE_RW_MMAP MAP_REGION2( \
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PLAT_QEMU_SP_IMAGE_HEAP_BASE, \
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PLAT_QEMU_SP_IMAGE_HEAP_BASE, \
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(QEMU_SP_IMAGE_STACK_TOTAL_SIZE + \
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PLAT_QEMU_SP_IMAGE_HEAP_SIZE), \
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MT_RW_DATA | MT_SECURE | \
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MT_USER, \
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PAGE_SIZE)
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/* Total number of memory regions with distinct properties */
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#define PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS 6
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/*
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* Name of the section to put the translation tables used by the S-EL1/S-EL0
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* context of a Secure Partition.
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*/
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "qemu_sp_xlat_table"
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#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "qemu_sp_xlat_table"
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/* Cookies passed to the Secure Partition at boot. Not used by QEMU platforms.*/
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#define PLAT_SPM_COOKIE_0 ULL(0)
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#define PLAT_SPM_COOKIE_1 ULL(0)
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#endif
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#define QEMU_PRI_BITS 2
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#define PLAT_SP_PRI 0x20
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#endif /* PLATFORM_DEF_H */
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2019, Linaro Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2020, Linaro Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -8,6 +8,12 @@ CRASH_REPORTING := 1
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include lib/libfdt/libfdt.mk
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ifeq (${SPM_MM},1)
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NEED_BL32 := yes
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EL3_EXCEPTION_HANDLING := 1
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GICV2_G0_FOR_EL3 := 1
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endif
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# Enable new version of image loading on QEMU platforms
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LOAD_IMAGE_V2 := 1
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@ -80,6 +86,9 @@ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
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${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \
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${QEMU_GIC_SOURCES}
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ifeq (${SPM_MM},1)
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BL31_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_spm.c
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endif
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SEPARATE_CODE_AND_RODATA := 1
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ENABLE_STACK_PROTECTOR := 0
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