Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into integration
* changes: doc: renesas: Update RZ/G2 code owner list plat: renesas: rzg: DT memory node enhancements renesas: rzg: emmc: Enable RZ/G2M support plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support drivers: renesas: rzg: Add HiHope RZ/G2M board support tools: renesas: Add tool support for RZ/G2 platforms
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
6b2924bbbf
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@ -15,6 +15,10 @@ tools/renesas/rcar_layout_create/*.bin
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tools/renesas/rcar_layout_create/*.srec
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tools/renesas/rcar_layout_create/*.map
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tools/renesas/rcar_layout_create/*.elf
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tools/renesas/rzg_layout_create/*.bin
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tools/renesas/rzg_layout_create/*.srec
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tools/renesas/rzg_layout_create/*.map
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tools/renesas/rzg_layout_create/*.elf
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tools/fiptool/fiptool
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tools/fiptool/fiptool.exe
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tools/cert_create/src/*.o
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@ -494,6 +494,8 @@ Renesas RZ/G2 platform port
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:G: `bijucdas`_
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:M: Marek Vasut <marek.vasut@gmail.com>
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:G: `marex`_
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:M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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:G: `prabhakarlad`_
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:F: docs/plat/rz-g2.rst
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:F: plat/renesas/common
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:F: plat/renesas/rzg
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@ -637,6 +639,7 @@ Build system
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.. _mtk09422: https://github.com/mtk09422
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.. _niej: https://github.com/niej
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.. _npoushin: https://github.com/npoushin
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.. _prabhakarlad: https://github.com/prabhakarlad
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.. _qoriq-open-source: https://github.com/qoriq-open-source
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.. _remi-triplefault: https://github.com/repk
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.. _rockchip-linux: https://github.com/rockchip-linux
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@ -11,11 +11,11 @@
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#define MMC_CH0 (0U) /* SDHI2/MMC0 */
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#define MMC_CH1 (1U) /* SDHI3/MMC1 */
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#if RCAR_LSI == RCAR_E3
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#define USE_MMC_CH (MMC_CH1) /* R-Car E3 */
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#else /* RCAR_LSI == RCAR_E3 */
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#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M)
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#define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2M */
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#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
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#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
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#endif /* RCAR_LSI == RCAR_E3 */
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#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
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#define BIT0 (0x00000001U)
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#define BIT1 (0x00000002U)
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@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include "board.h"
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#include "rcar_def.h"
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#ifndef BOARD_DEFAULT
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#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2M << BOARD_CODE_SHIFT)
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#endif /* BOARD_DEFAULT */
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#define BOARD_CODE_MASK (0xF8U)
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#define BOARD_REV_MASK (0x07U)
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#define BOARD_CODE_SHIFT (0x03)
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#define BOARD_ID_UNKNOWN (0xFFU)
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#define GPIO_INDT5 0xE605500C
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#define GP5_19_BIT (0x01U << 19)
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#define GP5_21_BIT (0x01U << 21)
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#define GP5_25_BIT (0x01U << 25)
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#define HM_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
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const char *g_board_tbl[] = {
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[BOARD_HIHOPE_RZ_G2M] = "HiHope RZ/G2M",
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[BOARD_UNKNOWN] = "unknown"
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};
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void rzg_get_board_type(uint32_t *type, uint32_t *rev)
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{
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static uint8_t board_id = BOARD_ID_UNKNOWN;
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const uint8_t board_tbl[][8] = {
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[BOARD_HIHOPE_RZ_G2M] = HM_ID,
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};
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uint32_t reg, boardInfo;
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if (board_id == BOARD_ID_UNKNOWN) {
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board_id = BOARD_DEFAULT;
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}
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*type = ((uint32_t) board_id & BOARD_CODE_MASK) >> BOARD_CODE_SHIFT;
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if (*type >= ARRAY_SIZE(board_tbl)) {
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/* no revision information, set Rev0.0. */
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*rev = 0;
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} else {
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reg = mmio_read_32(RCAR_PRR);
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if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
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*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
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} else {
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boardInfo = mmio_read_32(GPIO_INDT5) &
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(GP5_19_BIT | GP5_21_BIT);
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*rev = (((boardInfo & GP5_19_BIT) >> 14) |
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((boardInfo & GP5_21_BIT) >> 17)) + 0x30U;
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}
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}
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}
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@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RZ_G2_BOARD_H
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#define RZ_G2_BOARD_H
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enum rzg2_board_id {
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BOARD_HIHOPE_RZ_G2M = 0,
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BOARD_UNKNOWN
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};
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#define BOARD_REV_UNKNOWN (0xFFU)
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extern const char *g_board_tbl[];
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/************************************************************************
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* Revisions are expressed in 8 bits.
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* The upper 4 bits are major version.
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* The lower 4 bits are minor version.
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************************************************************************/
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#define GET_BOARD_MAJOR(a) ((uint32_t)(a) >> 0x4)
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#define GET_BOARD_MINOR(a) ((uint32_t)(a) & 0xF)
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#define GET_BOARD_NAME(a) (g_board_tbl[(a)])
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void rzg_get_board_type(uint32_t *type, uint32_t *rev);
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#endif /* RZ_G2_BOARD_H */
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@ -18,7 +18,7 @@ static void bl2_realtime_cpg_init_h3(void);
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static void bl2_system_cpg_init_h3(void);
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
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static void bl2_realtime_cpg_init_m3(void);
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static void bl2_system_cpg_init_m3(void);
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#endif
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@ -149,7 +149,7 @@ static void bl2_system_cpg_init_h3(void)
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}
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
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static void bl2_realtime_cpg_init_m3(void)
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{
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/* Realtime Module Stop Control Registers */
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@ -362,7 +362,7 @@ void bl2_cpg_init(void)
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}
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#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
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bl2_realtime_cpg_init_h3();
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#elif RCAR_LSI == RCAR_M3
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#elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
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bl2_realtime_cpg_init_m3();
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#elif RCAR_LSI == RCAR_M3N
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bl2_realtime_cpg_init_m3n();
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@ -408,7 +408,7 @@ void bl2_system_cpg_init(void)
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}
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#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
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bl2_system_cpg_init_h3();
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#elif RCAR_LSI == RCAR_M3
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#elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
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bl2_system_cpg_init_m3();
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#elif RCAR_LSI == RCAR_M3N
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bl2_system_cpg_init_m3n();
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@ -33,6 +33,7 @@ RCAR_H3N:=4
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RCAR_D3:=5
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RCAR_V3M:=6
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RCAR_AUTO:=99
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RZ_G2M:=100
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$(eval $(call add_define,RCAR_H3))
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$(eval $(call add_define,RCAR_M3))
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$(eval $(call add_define,RCAR_M3N))
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@ -41,6 +42,8 @@ $(eval $(call add_define,RCAR_H3N))
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$(eval $(call add_define,RCAR_D3))
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$(eval $(call add_define,RCAR_V3M))
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$(eval $(call add_define,RCAR_AUTO))
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$(eval $(call add_define,RZ_G2M))
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RCAR_CUT_10:=0
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RCAR_CUT_11:=1
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RCAR_CUT_13:=3
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@ -0,0 +1,909 @@
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/*
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* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <arch_helpers.h>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/console.h>
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#include <drivers/io/io_driver.h>
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#include <drivers/io/io_storage.h>
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#include <libfdt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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#include "avs_driver.h"
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#include "board.h"
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#include "boot_init_dram.h"
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#include "cpg_registers.h"
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#include "emmc_def.h"
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#include "emmc_hal.h"
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#include "emmc_std.h"
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#include "io_common.h"
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#include "io_rcar.h"
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#include "qos_init.h"
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#include "rcar_def.h"
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#include "rcar_private.h"
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#include "rcar_version.h"
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#include "rom_api.h"
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#define MAX_DRAM_CHANNELS 4
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/*
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* DDR ch0 has a shadow area mapped in 32bit address space.
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* Physical address 0x4_0000_0000 - 0x4_7fff_ffff in 64bit space
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* is mapped to 0x4000_0000 - 0xbfff_ffff in 32bit space.
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*/
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#define MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE 0x80000000ULL
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#if RCAR_BL2_DCACHE == 1
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/*
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* Following symbols are only used during plat_arch_setup() only
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* when RCAR_BL2_DCACHE is enabled.
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*/
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static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
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static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
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#if USE_COHERENT_MEM
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static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
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static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
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#endif /* USE_COHERENT_MEM */
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#endif /* RCAR_BL2_DCACHE */
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_init(void);
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extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
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extern void bl2_system_cpg_init(void);
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extern void bl2_secure_setting(void);
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extern void bl2_cpg_init(void);
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extern void rcar_io_emmc_setup(void);
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extern void rcar_io_setup(void);
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extern void rcar_swdt_release(void);
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extern void rcar_swdt_init(void);
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extern void rcar_rpc_init(void);
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extern void rcar_dma_init(void);
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extern void rzg_pfc_init(void);
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static void bl2_init_generic_timer(void);
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/* RZ/G2 product check */
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#if RCAR_LSI == RZ_G2M
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#define TARGET_PRODUCT PRR_PRODUCT_M3
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#define TARGET_NAME "RZ/G2M"
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#elif RCAR_LSI == RCAR_AUTO
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#define TARGET_NAME "RZ/G2M"
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#endif /* RCAR_LSI == RZ_G2M */
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#define GPIO_INDT (GPIO_INDT1)
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#define GPIO_BKUP_TRG_SHIFT (1U << 8U)
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CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
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< (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
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assert_bl31_params_do_not_fit_in_shared_memory);
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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|
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/* FDT with DRAM configuration */
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uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
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static void *fdt = (void *)fdt_blob;
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static void unsigned_num_print(uint64_t unum, unsigned int radix, char *string)
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{
|
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/* Just need enough space to store 64 bit decimal integer */
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char num_buf[20];
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int i = 0;
|
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unsigned int rem;
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|
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do {
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rem = unum % radix;
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if (rem < 0xaU) {
|
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num_buf[i] = '0' + rem;
|
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} else {
|
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num_buf[i] = 'a' + (rem - 0xaU);
|
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}
|
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i++;
|
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unum /= radix;
|
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} while (unum > 0U);
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|
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while (--i >= 0) {
|
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*string++ = num_buf[i];
|
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}
|
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*string = 0;
|
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}
|
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|
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#if RCAR_LOSSY_ENABLE == 1
|
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typedef struct bl2_lossy_info {
|
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uint32_t magic;
|
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uint32_t a0;
|
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uint32_t b0;
|
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} bl2_lossy_info_t;
|
||||
|
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static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
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uint64_t end_addr, uint32_t format,
|
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uint32_t enable, int fcnlnode)
|
||||
{
|
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const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
|
||||
char nodename[40] = { 0 };
|
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int ret, node;
|
||||
|
||||
/* Ignore undefined addresses */
|
||||
if (start_addr == 0UL && end_addr == 0UL) {
|
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return;
|
||||
}
|
||||
|
||||
snprintf(nodename, sizeof(nodename), "lossy-decompression@");
|
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unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
|
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|
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node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
|
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if (ret < 0) {
|
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NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
ret = fdt_setprop_string(fdt, node, "compatible",
|
||||
"renesas,lossy-decompression");
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot add FCNL compat string %s (ret=%i)\n",
|
||||
"renesas,lossy-decompression", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
ret = fdt_appendprop_string(fdt, node, "compatible",
|
||||
"shared-dma-pool");
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot append FCNL compat string %s (ret=%i)\n",
|
||||
"shared-dma-pool", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
||||
static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
|
||||
uint64_t end_addr, uint32_t format,
|
||||
uint32_t enable, int fcnlnode)
|
||||
{
|
||||
bl2_lossy_info_t info;
|
||||
uint32_t reg;
|
||||
|
||||
bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
|
||||
|
||||
reg = format | (start_addr >> 20);
|
||||
mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg);
|
||||
mmio_write_32(AXI_DCMPAREACRB0 + 0x8U * no, end_addr >> 20);
|
||||
mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable);
|
||||
|
||||
info.magic = 0x12345678U;
|
||||
info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no);
|
||||
info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no);
|
||||
|
||||
mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
|
||||
mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4U, info.a0);
|
||||
mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8U, info.b0);
|
||||
|
||||
NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
|
||||
mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no),
|
||||
mmio_read_32(AXI_DCMPAREACRB0 + 0x8U * no));
|
||||
}
|
||||
#endif /* RCAR_LOSSY_ENABLE == 1 */
|
||||
|
||||
void bl2_plat_flush_bl31_params(void)
|
||||
{
|
||||
uint32_t product_cut, product, cut;
|
||||
uint32_t boot_dev, boot_cpu;
|
||||
uint32_t reg;
|
||||
|
||||
reg = mmio_read_32(RCAR_MODEMR);
|
||||
boot_dev = reg & MODEMR_BOOT_DEV_MASK;
|
||||
|
||||
if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
|
||||
boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
|
||||
emmc_terminate();
|
||||
}
|
||||
|
||||
if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7) {
|
||||
bl2_secure_setting();
|
||||
}
|
||||
|
||||
reg = mmio_read_32(RCAR_PRR);
|
||||
product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
|
||||
product = reg & PRR_PRODUCT_MASK;
|
||||
cut = reg & PRR_CUT_MASK;
|
||||
|
||||
if (!((product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) ||
|
||||
(product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20))) {
|
||||
/* Disable MFIS write protection */
|
||||
mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1U);
|
||||
}
|
||||
|
||||
reg = mmio_read_32(RCAR_MODEMR);
|
||||
boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
|
||||
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
|
||||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
|
||||
if (product_cut == PRR_PRODUCT_H3_CUT20) {
|
||||
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
} else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
|
||||
product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
|
||||
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
} else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
|
||||
(product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
|
||||
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
}
|
||||
|
||||
if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
|
||||
product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
|
||||
product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
|
||||
product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
|
||||
mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
|
||||
mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
|
||||
mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
|
||||
|
||||
rcar_swdt_release();
|
||||
bl2_system_cpg_init();
|
||||
|
||||
#if RCAR_BL2_DCACHE == 1
|
||||
/* Disable data cache (clean and invalidate) */
|
||||
disable_mmu_el3();
|
||||
#endif /* RCAR_BL2_DCACHE == 1 */
|
||||
}
|
||||
|
||||
static uint32_t is_ddr_backup_mode(void)
|
||||
{
|
||||
#if RCAR_SYSTEM_SUSPEND
|
||||
static uint32_t reason = RCAR_COLD_BOOT;
|
||||
static uint32_t once;
|
||||
|
||||
if (once != 0U) {
|
||||
return reason;
|
||||
}
|
||||
|
||||
once = 1;
|
||||
if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0U) {
|
||||
return reason;
|
||||
}
|
||||
|
||||
reason = RCAR_WARM_BOOT;
|
||||
return reason;
|
||||
#else /* RCAR_SYSTEM_SUSPEND */
|
||||
return RCAR_COLD_BOOT;
|
||||
#endif /* RCAR_SYSTEM_SUSPEND */
|
||||
}
|
||||
|
||||
int bl2_plat_handle_pre_image_load(unsigned int image_id)
|
||||
{
|
||||
u_register_t *boot_kind = (void *)BOOT_KIND_BASE;
|
||||
bl_mem_params_node_t *bl_mem_params;
|
||||
|
||||
if (image_id != BL31_IMAGE_ID) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
|
||||
if (is_ddr_backup_mode() != RCAR_COLD_BOOT) {
|
||||
*boot_kind = RCAR_WARM_BOOT;
|
||||
flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
|
||||
|
||||
console_flush();
|
||||
bl2_plat_flush_bl31_params();
|
||||
|
||||
/* will not return */
|
||||
bl2_enter_bl31(&bl_mem_params->ep_info);
|
||||
}
|
||||
|
||||
*boot_kind = RCAR_COLD_BOOT;
|
||||
flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uint64_t rzg_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest)
|
||||
{
|
||||
uint32_t cert, len;
|
||||
int err;
|
||||
|
||||
err = rcar_get_certificate(certid, &cert);
|
||||
if (err != 0) {
|
||||
ERROR("%s : cert file load error", __func__);
|
||||
return 1U;
|
||||
}
|
||||
|
||||
rcar_read_certificate((uint64_t)cert, &len, dest);
|
||||
|
||||
return 0U;
|
||||
}
|
||||
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
static bl2_to_bl31_params_mem_t *params;
|
||||
bl_mem_params_node_t *bl_mem_params;
|
||||
uintptr_t dest;
|
||||
uint64_t ret;
|
||||
|
||||
if (params == NULL) {
|
||||
params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
|
||||
memset((void *)PARAMS_BASE, 0, sizeof(*params));
|
||||
}
|
||||
|
||||
bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
|
||||
switch (image_id) {
|
||||
case BL31_IMAGE_ID:
|
||||
ret = rzg_get_dest_addr_from_cert(SOC_FW_CONTENT_CERT_ID,
|
||||
&dest);
|
||||
if (ret == 0U) {
|
||||
bl_mem_params->image_info.image_base = dest;
|
||||
}
|
||||
break;
|
||||
case BL32_IMAGE_ID:
|
||||
ret = rzg_get_dest_addr_from_cert(TRUSTED_OS_FW_CONTENT_CERT_ID,
|
||||
&dest);
|
||||
if (ret == 0U) {
|
||||
bl_mem_params->image_info.image_base = dest;
|
||||
}
|
||||
|
||||
memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
|
||||
sizeof(entry_point_info_t));
|
||||
break;
|
||||
case BL33_IMAGE_ID:
|
||||
memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
|
||||
sizeof(entry_point_info_t));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct meminfo *bl2_plat_sec_mem_layout(void)
|
||||
{
|
||||
return &bl2_tzram_layout;
|
||||
}
|
||||
|
||||
static void bl2_populate_compatible_string(void *dt)
|
||||
{
|
||||
uint32_t board_type;
|
||||
uint32_t board_rev;
|
||||
uint32_t reg;
|
||||
int ret;
|
||||
|
||||
fdt_setprop_u32(dt, 0, "#address-cells", 2);
|
||||
fdt_setprop_u32(dt, 0, "#size-cells", 2);
|
||||
|
||||
/* Populate compatible string */
|
||||
rzg_get_board_type(&board_type, &board_rev);
|
||||
switch (board_type) {
|
||||
case BOARD_HIHOPE_RZ_G2M:
|
||||
ret = fdt_setprop_string(dt, 0, "compatible",
|
||||
"hoperun,hihope-rzg2m");
|
||||
break;
|
||||
default:
|
||||
NOTICE("BL2: Cannot set compatible string, board unsupported\n");
|
||||
panic();
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
reg = mmio_read_32(RCAR_PRR);
|
||||
switch (reg & PRR_PRODUCT_MASK) {
|
||||
case PRR_PRODUCT_M3:
|
||||
ret = fdt_appendprop_string(dt, 0, "compatible",
|
||||
"renesas,r8a774a1");
|
||||
break;
|
||||
default:
|
||||
NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
|
||||
panic();
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret < 0) {
|
||||
NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
||||
static int bl2_add_memory_node(uint64_t start, uint64_t size)
|
||||
{
|
||||
char nodename[32] = { 0 };
|
||||
uint64_t fdtsize;
|
||||
int ret, node;
|
||||
|
||||
fdtsize = cpu_to_fdt64(size);
|
||||
|
||||
snprintf(nodename, sizeof(nodename), "memory@");
|
||||
unsigned_num_print(start, 16, nodename + strlen(nodename));
|
||||
node = ret = fdt_add_subnode(fdt, 0, nodename);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_string(fdt, node, "device_type", "memory");
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_u64(fdt, node, "reg", start);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return fdt_appendprop(fdt, node, "reg", &fdtsize, sizeof(fdtsize));
|
||||
}
|
||||
|
||||
static void bl2_advertise_dram_entries(uint64_t dram_config[8])
|
||||
{
|
||||
uint64_t start, size;
|
||||
int ret, chan;
|
||||
|
||||
for (chan = 0; chan < MAX_DRAM_CHANNELS; chan++) {
|
||||
start = dram_config[2 * chan];
|
||||
size = dram_config[2 * chan + 1];
|
||||
if (size == 0U) {
|
||||
continue;
|
||||
}
|
||||
|
||||
NOTICE("BL2: CH%d: %llx - %llx, %lld %siB\n",
|
||||
chan, start, start + size - 1U,
|
||||
(size >> 30) ? : size >> 20,
|
||||
(size >> 30) ? "G" : "M");
|
||||
}
|
||||
|
||||
/*
|
||||
* We add the DT nodes in reverse order here. The fdt_add_subnode()
|
||||
* adds the DT node before the first existing DT node, so we have
|
||||
* to add them in reverse order to get nodes sorted by address in
|
||||
* the resulting DT.
|
||||
*/
|
||||
for (chan = MAX_DRAM_CHANNELS - 1; chan >= 0; chan--) {
|
||||
start = dram_config[2 * chan];
|
||||
size = dram_config[2 * chan + 1];
|
||||
if (size == 0U) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Channel 0 is mapped in 32bit space and the first
|
||||
* 128 MiB are reserved
|
||||
*/
|
||||
if (chan == 0) {
|
||||
/*
|
||||
* Maximum DDR size in Channel 0 for 32 bit space is 2GB, Add DT node
|
||||
* for remaining region in 64 bit address space
|
||||
*/
|
||||
if (size > MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE) {
|
||||
start = dram_config[chan] + MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE;
|
||||
size -= MAX_DRAM_SIZE_CH0_32BIT_ADDR_SPACE;
|
||||
ret = bl2_add_memory_node(start, size);
|
||||
if (ret < 0) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
start = 0x48000000U;
|
||||
size -= 0x8000000U;
|
||||
}
|
||||
|
||||
ret = bl2_add_memory_node(start, size);
|
||||
if (ret < 0) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
err:
|
||||
NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
static void bl2_advertise_dram_size(uint32_t product)
|
||||
{
|
||||
uint64_t dram_config[8] = {
|
||||
[0] = 0x400000000ULL,
|
||||
[2] = 0x500000000ULL,
|
||||
[4] = 0x600000000ULL,
|
||||
[6] = 0x700000000ULL,
|
||||
};
|
||||
|
||||
switch (product) {
|
||||
case PRR_PRODUCT_M3:
|
||||
/* 4GB(2GBx2 2ch split) */
|
||||
dram_config[1] = 0x80000000ULL;
|
||||
dram_config[5] = 0x80000000ULL;
|
||||
break;
|
||||
default:
|
||||
NOTICE("BL2: Detected invalid DRAM entries\n");
|
||||
break;
|
||||
}
|
||||
|
||||
bl2_advertise_dram_entries(dram_config);
|
||||
}
|
||||
|
||||
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4)
|
||||
{
|
||||
uint32_t reg, midr, boot_dev, boot_cpu, type, rev;
|
||||
uint32_t product, product_cut, major, minor;
|
||||
int32_t ret;
|
||||
const char *str;
|
||||
const char *unknown = "unknown";
|
||||
const char *cpu_ca57 = "CA57";
|
||||
const char *cpu_ca53 = "CA53";
|
||||
const char *product_g2m = "G2M";
|
||||
const char *boot_hyper80 = "HyperFlash(80MHz)";
|
||||
const char *boot_qspi40 = "QSPI Flash(40MHz)";
|
||||
const char *boot_qspi80 = "QSPI Flash(80MHz)";
|
||||
const char *boot_emmc25x1 = "eMMC(25MHz x1)";
|
||||
const char *boot_emmc50x8 = "eMMC(50MHz x8)";
|
||||
const char *boot_hyper160 = "HyperFlash(160MHz)";
|
||||
#if RZG_LCS_STATE_DETECTION_ENABLE
|
||||
uint32_t lcs;
|
||||
const char *lcs_secure = "SE";
|
||||
const char *lcs_cm = "CM";
|
||||
const char *lcs_dm = "DM";
|
||||
const char *lcs_sd = "SD";
|
||||
const char *lcs_fa = "FA";
|
||||
#endif /* RZG_LCS_STATE_DETECTION_ENABLE */
|
||||
|
||||
#if (RCAR_LOSSY_ENABLE == 1)
|
||||
int fcnlnode;
|
||||
#endif /* (RCAR_LOSSY_ENABLE == 1) */
|
||||
|
||||
bl2_init_generic_timer();
|
||||
|
||||
reg = mmio_read_32(RCAR_MODEMR);
|
||||
boot_dev = reg & MODEMR_BOOT_DEV_MASK;
|
||||
boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
|
||||
|
||||
bl2_cpg_init();
|
||||
|
||||
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
|
||||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
|
||||
rzg_pfc_init();
|
||||
rcar_console_boot_init();
|
||||
}
|
||||
|
||||
plat_rcar_gic_driver_init();
|
||||
plat_rcar_gic_init();
|
||||
rcar_swdt_init();
|
||||
|
||||
/* FIQ interrupts are taken to EL3 */
|
||||
write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
|
||||
|
||||
write_daifclr(DAIF_FIQ_BIT);
|
||||
|
||||
reg = read_midr();
|
||||
midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
|
||||
switch (midr) {
|
||||
case MIDR_CA57:
|
||||
str = cpu_ca57;
|
||||
break;
|
||||
case MIDR_CA53:
|
||||
str = cpu_ca53;
|
||||
break;
|
||||
default:
|
||||
str = unknown;
|
||||
break;
|
||||
}
|
||||
|
||||
NOTICE("BL2: RZ/G2 Initial Program Loader(%s) Rev.%s\n", str,
|
||||
version_of_renesas);
|
||||
|
||||
reg = mmio_read_32(RCAR_PRR);
|
||||
product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
|
||||
product = reg & PRR_PRODUCT_MASK;
|
||||
|
||||
switch (product) {
|
||||
case PRR_PRODUCT_M3:
|
||||
str = product_g2m;
|
||||
break;
|
||||
default:
|
||||
str = unknown;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((product == PRR_PRODUCT_M3) &&
|
||||
((reg & RCAR_MAJOR_MASK) == PRR_PRODUCT_20)) {
|
||||
if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
|
||||
/* M3 Ver.1.1 or Ver.1.2 */
|
||||
NOTICE("BL2: PRR is RZ/%s Ver.1.1 / Ver.1.2\n", str);
|
||||
} else {
|
||||
NOTICE("BL2: PRR is RZ/%s Ver.1.%d\n", str,
|
||||
(reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
|
||||
}
|
||||
} else {
|
||||
major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
|
||||
major = major + RCAR_MAJOR_OFFSET;
|
||||
minor = reg & RCAR_MINOR_MASK;
|
||||
NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
|
||||
}
|
||||
|
||||
rzg_get_board_type(&type, &rev);
|
||||
|
||||
switch (type) {
|
||||
case BOARD_HIHOPE_RZ_G2M:
|
||||
break;
|
||||
default:
|
||||
type = BOARD_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN) {
|
||||
NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
|
||||
} else {
|
||||
NOTICE("BL2: Board is %s Rev.%d.%d\n",
|
||||
GET_BOARD_NAME(type),
|
||||
GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
|
||||
}
|
||||
|
||||
#if RCAR_LSI != RCAR_AUTO
|
||||
if (product != TARGET_PRODUCT) {
|
||||
ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
|
||||
ERROR("BL2: Please write the correct IPL to flash memory.\n");
|
||||
panic();
|
||||
}
|
||||
#endif /* RCAR_LSI != RCAR_AUTO */
|
||||
rcar_avs_init();
|
||||
rcar_avs_setting();
|
||||
|
||||
switch (boot_dev) {
|
||||
case MODEMR_BOOT_DEV_HYPERFLASH160:
|
||||
str = boot_hyper160;
|
||||
break;
|
||||
case MODEMR_BOOT_DEV_HYPERFLASH80:
|
||||
str = boot_hyper80;
|
||||
break;
|
||||
case MODEMR_BOOT_DEV_QSPI_FLASH40:
|
||||
str = boot_qspi40;
|
||||
break;
|
||||
case MODEMR_BOOT_DEV_QSPI_FLASH80:
|
||||
str = boot_qspi80;
|
||||
break;
|
||||
case MODEMR_BOOT_DEV_EMMC_25X1:
|
||||
str = boot_emmc25x1;
|
||||
break;
|
||||
case MODEMR_BOOT_DEV_EMMC_50X8:
|
||||
str = boot_emmc50x8;
|
||||
break;
|
||||
default:
|
||||
str = unknown;
|
||||
break;
|
||||
}
|
||||
NOTICE("BL2: Boot device is %s\n", str);
|
||||
|
||||
rcar_avs_setting();
|
||||
|
||||
#if RZG_LCS_STATE_DETECTION_ENABLE
|
||||
reg = rcar_rom_get_lcs(&lcs);
|
||||
if (reg != 0U) {
|
||||
str = unknown;
|
||||
goto lcm_state;
|
||||
}
|
||||
|
||||
switch (lcs) {
|
||||
case LCS_CM:
|
||||
str = lcs_cm;
|
||||
break;
|
||||
case LCS_DM:
|
||||
str = lcs_dm;
|
||||
break;
|
||||
case LCS_SD:
|
||||
str = lcs_sd;
|
||||
break;
|
||||
case LCS_SE:
|
||||
str = lcs_secure;
|
||||
break;
|
||||
case LCS_FA:
|
||||
str = lcs_fa;
|
||||
break;
|
||||
default:
|
||||
str = unknown;
|
||||
break;
|
||||
}
|
||||
|
||||
lcm_state:
|
||||
NOTICE("BL2: LCM state is %s\n", str);
|
||||
#endif /* RZG_LCS_STATE_DETECTION_ENABLE */
|
||||
|
||||
rcar_avs_end();
|
||||
is_ddr_backup_mode();
|
||||
|
||||
bl2_tzram_layout.total_base = BL31_BASE;
|
||||
bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
|
||||
|
||||
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
|
||||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
|
||||
ret = rzg_dram_init();
|
||||
if (ret != 0) {
|
||||
NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
|
||||
panic();
|
||||
}
|
||||
rzg_qos_init();
|
||||
}
|
||||
|
||||
/* Set up FDT */
|
||||
ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
|
||||
if (ret != 0) {
|
||||
NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
/* Add platform compatible string */
|
||||
bl2_populate_compatible_string(fdt);
|
||||
|
||||
/* Print DRAM layout */
|
||||
bl2_advertise_dram_size(product);
|
||||
|
||||
if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
|
||||
boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
|
||||
if (rcar_emmc_init() != EMMC_SUCCESS) {
|
||||
NOTICE("BL2: Failed to eMMC driver initialize.\n");
|
||||
panic();
|
||||
}
|
||||
rcar_emmc_memcard_power(EMMC_POWER_ON);
|
||||
if (rcar_emmc_mount() != EMMC_SUCCESS) {
|
||||
NOTICE("BL2: Failed to eMMC mount operation.\n");
|
||||
panic();
|
||||
}
|
||||
} else {
|
||||
rcar_rpc_init();
|
||||
rcar_dma_init();
|
||||
}
|
||||
|
||||
reg = mmio_read_32(RST_WDTRSTCR);
|
||||
reg &= ~WDTRSTCR_RWDT_RSTMSK;
|
||||
reg |= WDTRSTCR_PASSWORD;
|
||||
mmio_write_32(RST_WDTRSTCR, reg);
|
||||
|
||||
mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
|
||||
mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
|
||||
|
||||
reg = mmio_read_32(RCAR_PRR);
|
||||
if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57) {
|
||||
mmio_write_32(CPG_CA57DBGRCR,
|
||||
DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
|
||||
}
|
||||
|
||||
if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53) {
|
||||
mmio_write_32(CPG_CA53DBGRCR,
|
||||
DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
|
||||
}
|
||||
|
||||
if (product_cut == PRR_PRODUCT_H3_CUT10) {
|
||||
reg = mmio_read_32(CPG_PLL2CR);
|
||||
reg &= ~((uint32_t)1 << 5);
|
||||
mmio_write_32(CPG_PLL2CR, reg);
|
||||
|
||||
reg = mmio_read_32(CPG_PLL4CR);
|
||||
reg &= ~((uint32_t)1 << 5);
|
||||
mmio_write_32(CPG_PLL4CR, reg);
|
||||
|
||||
reg = mmio_read_32(CPG_PLL0CR);
|
||||
reg &= ~((uint32_t)1 << 12);
|
||||
mmio_write_32(CPG_PLL0CR, reg);
|
||||
}
|
||||
#if (RCAR_LOSSY_ENABLE == 1)
|
||||
NOTICE("BL2: Lossy Decomp areas\n");
|
||||
|
||||
fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
|
||||
if (fcnlnode < 0) {
|
||||
NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
|
||||
fcnlnode);
|
||||
panic();
|
||||
}
|
||||
|
||||
bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
|
||||
LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
|
||||
bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
|
||||
LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
|
||||
bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
|
||||
LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
|
||||
#endif /* RCAR_LOSSY_ENABLE */
|
||||
|
||||
fdt_pack(fdt);
|
||||
NOTICE("BL2: FDT at %p\n", fdt);
|
||||
|
||||
if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
|
||||
boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
|
||||
rcar_io_emmc_setup();
|
||||
} else {
|
||||
rcar_io_setup();
|
||||
}
|
||||
}
|
||||
|
||||
void bl2_el3_plat_arch_setup(void)
|
||||
{
|
||||
#if RCAR_BL2_DCACHE == 1
|
||||
NOTICE("BL2: D-Cache enable\n");
|
||||
rcar_configure_mmu_el3(BL2_BASE,
|
||||
BL2_END - BL2_BASE,
|
||||
BL2_RO_BASE, BL2_RO_LIMIT
|
||||
#if USE_COHERENT_MEM
|
||||
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
|
||||
#endif /* USE_COHERENT_MEM */
|
||||
);
|
||||
#endif /* RCAR_BL2_DCACHE == 1 */
|
||||
}
|
||||
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
/*
|
||||
* Place holder for performing any platform initialization specific
|
||||
* to BL2.
|
||||
*/
|
||||
}
|
||||
|
||||
static void bl2_init_generic_timer(void)
|
||||
{
|
||||
uint32_t reg_cntfid;
|
||||
uint32_t modemr;
|
||||
uint32_t modemr_pll;
|
||||
uint32_t pll_table[] = {
|
||||
EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
|
||||
EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
|
||||
EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
|
||||
EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
|
||||
};
|
||||
|
||||
modemr = mmio_read_32(RCAR_MODEMR);
|
||||
modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
|
||||
|
||||
/* Set frequency data in CNTFID0 */
|
||||
reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
|
||||
|
||||
/* Update memory mapped and register based frequency */
|
||||
write_cntfrq_el0((u_register_t)reg_cntfid);
|
||||
mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
|
||||
/* Enable counter */
|
||||
mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
|
||||
(uint32_t)CNTCR_EN);
|
||||
}
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
#
|
||||
# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include plat/renesas/common/common.mk
|
||||
|
||||
ifndef LSI
|
||||
$(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI")
|
||||
else
|
||||
ifeq (${LSI},AUTO)
|
||||
RCAR_LSI:=${RCAR_AUTO}
|
||||
else ifeq (${LSI},G2M)
|
||||
RCAR_LSI:=${RZ_G2M}
|
||||
ifndef LSI_CUT
|
||||
# enable compatible function.
|
||||
RCAR_LSI_CUT_COMPAT := 1
|
||||
$(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
|
||||
else
|
||||
# disable compatible function.
|
||||
ifeq (${LSI_CUT},10)
|
||||
RCAR_LSI_CUT:=0
|
||||
else ifeq (${LSI_CUT},11)
|
||||
RCAR_LSI_CUT:=1
|
||||
else ifeq (${LSI_CUT},13)
|
||||
RCAR_LSI_CUT:=3
|
||||
else ifeq (${LSI_CUT},30)
|
||||
RCAR_LSI_CUT:=20
|
||||
else
|
||||
$(error "Error: ${LSI_CUT} is not supported.")
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_LSI_CUT))
|
||||
endif
|
||||
else
|
||||
$(error "Error: ${LSI} is not supported.")
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_LSI))
|
||||
endif
|
||||
|
||||
# Process RZG_LCS_STATE_DETECTION_ENABLE flag
|
||||
# Enable to get LCS state information
|
||||
ifndef RZG_LCS_STATE_DETECTION_ENABLE
|
||||
RZG_LCS_STATE_DETECTION_ENABLE := 0
|
||||
endif
|
||||
$(eval $(call add_define,RZG_LCS_STATE_DETECTION_ENABLE))
|
||||
|
||||
# Process RCAR_SECURE_BOOT flag
|
||||
ifndef RCAR_SECURE_BOOT
|
||||
RCAR_SECURE_BOOT := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_SECURE_BOOT))
|
||||
|
||||
# LCS state of RZ/G2 Chip is all CM.
|
||||
# However certain chips(RZ/G2M and RZ/G2E) have incorrect factory Fuse settings
|
||||
# which results in getting incorrect LCS states
|
||||
# if need to enable RCAR_SECURE_BOOT, make sure the chip has proper factory Fuse settings.
|
||||
ifeq (${RCAR_SECURE_BOOT},1)
|
||||
ifeq (${RZG_LCS_STATE_DETECTION_ENABLE},0)
|
||||
$(error "Error: Please check the chip has proper factory Fuse settings and set RZG_LCS_STATE_DETECTION_ENABLE to enable.")
|
||||
endif
|
||||
endif
|
||||
|
||||
# lock RPC HYPERFLASH access by default
|
||||
# unlock to repogram the ATF firmware from u-boot
|
||||
ifndef RCAR_RPC_HYPERFLASH_LOCKED
|
||||
RCAR_RPC_HYPERFLASH_LOCKED := 1
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED))
|
||||
|
||||
# Process RCAR_QOS_TYPE flag
|
||||
ifndef RCAR_QOS_TYPE
|
||||
RCAR_QOS_TYPE := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_QOS_TYPE))
|
||||
|
||||
# Process RCAR_DRAM_SPLIT flag
|
||||
ifndef RCAR_DRAM_SPLIT
|
||||
RCAR_DRAM_SPLIT := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_DRAM_SPLIT))
|
||||
|
||||
# Process RCAR_BL33_EXECUTION_EL flag
|
||||
ifndef RCAR_BL33_EXECUTION_EL
|
||||
RCAR_BL33_EXECUTION_EL := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_BL33_EXECUTION_EL))
|
||||
|
||||
# Process RCAR_AVS_SETTING_ENABLE flag
|
||||
ifndef AVS_SETTING_ENABLE
|
||||
AVS_SETTING_ENABLE := 0
|
||||
endif
|
||||
$(eval $(call add_define,AVS_SETTING_ENABLE))
|
||||
|
||||
# Process RCAR_LOSSY_ENABLE flag
|
||||
ifndef RCAR_LOSSY_ENABLE
|
||||
RCAR_LOSSY_ENABLE := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_LOSSY_ENABLE))
|
||||
|
||||
# Process LIFEC_DBSC_PROTECT_ENABLE flag
|
||||
ifndef LIFEC_DBSC_PROTECT_ENABLE
|
||||
LIFEC_DBSC_PROTECT_ENABLE := 1
|
||||
endif
|
||||
$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE))
|
||||
|
||||
# Process RCAR_GEN3_ULCB flag
|
||||
ifndef RCAR_GEN3_ULCB
|
||||
RCAR_GEN3_ULCB := 0
|
||||
endif
|
||||
|
||||
# Process RCAR_REF_INT flag
|
||||
ifndef RCAR_REF_INT
|
||||
RCAR_REF_INT :=0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_REF_INT))
|
||||
|
||||
# Process RCAR_REWT_TRAINING flag
|
||||
ifndef RCAR_REWT_TRAINING
|
||||
RCAR_REWT_TRAINING := 1
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_REWT_TRAINING))
|
||||
|
||||
# Process RCAR_SYSTEM_SUSPEND flag
|
||||
ifndef RCAR_SYSTEM_SUSPEND
|
||||
RCAR_SYSTEM_SUSPEND := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_SYSTEM_SUSPEND))
|
||||
|
||||
# Process RCAR_DRAM_LPDDR4_MEMCONF flag
|
||||
ifndef RCAR_DRAM_LPDDR4_MEMCONF
|
||||
RCAR_DRAM_LPDDR4_MEMCONF :=1
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF))
|
||||
|
||||
# Process RCAR_DRAM_DDR3L_MEMCONF flag
|
||||
ifndef RCAR_DRAM_DDR3L_MEMCONF
|
||||
RCAR_DRAM_DDR3L_MEMCONF :=1
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF))
|
||||
|
||||
# Process RCAR_DRAM_DDR3L_MEMDUAL flag
|
||||
ifndef RCAR_DRAM_DDR3L_MEMDUAL
|
||||
RCAR_DRAM_DDR3L_MEMDUAL :=1
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL))
|
||||
|
||||
# Process RCAR_BL33_ARG0 flag
|
||||
ifdef RCAR_BL33_ARG0
|
||||
$(eval $(call add_define,RCAR_BL33_ARG0))
|
||||
endif
|
||||
|
||||
#Process RCAR_BL2_DCACHE flag
|
||||
ifndef RCAR_BL2_DCACHE
|
||||
RCAR_BL2_DCACHE := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_BL2_DCACHE))
|
||||
|
||||
# Process RCAR_DRAM_CHANNEL flag
|
||||
ifndef RCAR_DRAM_CHANNEL
|
||||
RCAR_DRAM_CHANNEL :=15
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_DRAM_CHANNEL))
|
||||
|
||||
#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag
|
||||
ifndef RCAR_SYSTEM_RESET_KEEPON_DDR
|
||||
RCAR_SYSTEM_RESET_KEEPON_DDR := 0
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
|
||||
|
||||
include drivers/renesas/rzg/ddr/ddr.mk
|
||||
include drivers/renesas/rzg/qos/qos.mk
|
||||
include drivers/renesas/rzg/pfc/pfc.mk
|
||||
include lib/libfdt/libfdt.mk
|
||||
|
||||
PLAT_INCLUDES += -Idrivers/renesas/rzg/ddr \
|
||||
-Idrivers/renesas/rzg/qos \
|
||||
-Idrivers/renesas/rzg/board \
|
||||
-Idrivers/renesas/common \
|
||||
-Idrivers/renesas/common/iic_dvfs \
|
||||
-Idrivers/renesas/common/avs \
|
||||
-Idrivers/renesas/common/delay \
|
||||
-Idrivers/renesas/common/rom \
|
||||
-Idrivers/renesas/common/scif \
|
||||
-Idrivers/renesas/common/emmc \
|
||||
-Idrivers/renesas/common/pwrc \
|
||||
-Idrivers/renesas/common/io
|
||||
|
||||
BL2_SOURCES += plat/renesas/rzg/bl2_plat_setup.c \
|
||||
drivers/renesas/rzg/board/board.c
|
||||
|
||||
# build the layout images for the bootrom and the necessary srecords
|
||||
rzg: rzg_layout_create rzg_srecord
|
||||
distclean realclean clean: clean_layout_tool clean_srecord
|
||||
|
||||
# layout images
|
||||
LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create
|
||||
|
||||
clean_layout_tool:
|
||||
@echo "clean layout tool"
|
||||
${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean
|
||||
|
||||
.PHONY: rzg_layout_create
|
||||
rzg_layout_create:
|
||||
@echo "generating layout srecs"
|
||||
${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
|
||||
|
||||
# srecords
|
||||
SREC_PATH = ${BUILD_PLAT}
|
||||
BL2_ELF_SRC = ${SREC_PATH}/bl2/bl2.elf
|
||||
BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf
|
||||
|
||||
clean_srecord:
|
||||
@echo "clean bl2 and bl31 srecs"
|
||||
rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
|
||||
|
||||
.PHONY: rzg_srecord
|
||||
rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
|
||||
@echo "generating srec: ${SREC_PATH}/bl2.srec"
|
||||
$(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec
|
||||
@echo "generating srec: ${SREC_PATH}/bl31.srec"
|
||||
$(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
#
|
||||
# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
###################################################
|
||||
# makefile
|
||||
###################################################
|
||||
|
||||
#output file name
|
||||
FILE_NAME_SA0 = bootparam_sa0
|
||||
FILE_NAME_SA6 = cert_header_sa6
|
||||
|
||||
OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
|
||||
OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf
|
||||
|
||||
#object file name
|
||||
OBJ_FILE_SA0 = sa0.o
|
||||
OBJ_FILE_SA6 = sa6.o
|
||||
|
||||
#linker script name
|
||||
MEMORY_DEF_SA0 = sa0.ld.S
|
||||
MEMORY_DEF_SA6 = sa6.ld.S
|
||||
|
||||
###################################################
|
||||
# Convenience function for adding build definitions
|
||||
# $(eval $(call add_define,FOO)) will have:
|
||||
# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
|
||||
define add_define
|
||||
DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
|
||||
endef
|
||||
|
||||
# Process RCAR_SA0_SIZE flag
|
||||
ifndef RCAR_SA0_SIZE
|
||||
RCAR_SA0_SIZE := 1
|
||||
else
|
||||
ifeq (${RCAR_SA0_SIZE},0)
|
||||
RCAR_SA0_SIZE := 0
|
||||
else
|
||||
RCAR_SA0_SIZE := 1
|
||||
endif
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_SA0_SIZE))
|
||||
|
||||
# Process RCAR_SA6_TYPE flag
|
||||
ifndef RCAR_SA6_TYPE
|
||||
RCAR_SA6_TYPE := 0
|
||||
else
|
||||
ifeq (${RCAR_SA6_TYPE},0)
|
||||
RCAR_SA6_TYPE := 0
|
||||
else
|
||||
RCAR_SA6_TYPE := 1
|
||||
endif
|
||||
endif
|
||||
$(eval $(call add_define,RCAR_SA6_TYPE))
|
||||
|
||||
RCAR_VMA_ADJUST_ADDR := 0xE6320000
|
||||
$(eval $(call add_define,RCAR_VMA_ADJUST_ADDR))
|
||||
|
||||
|
||||
###################################################
|
||||
|
||||
#c compiler
|
||||
CC = $(CROSS_COMPILE)gcc
|
||||
CFLAGS += ${DEFINES}
|
||||
CFLAGS += -nostdinc \
|
||||
-I../../../include/lib/libc \
|
||||
-I../../../include/lib/libc/aarch64
|
||||
|
||||
#Linker
|
||||
LD = $(CROSS_COMPILE)ld
|
||||
|
||||
#objcopy
|
||||
objcopy = $(CROSS_COMPILE)objcopy
|
||||
|
||||
#clean
|
||||
CL = rm -f
|
||||
|
||||
###################################################
|
||||
.SUFFIXES : .s .c .o
|
||||
|
||||
###################################################
|
||||
# command
|
||||
|
||||
.PHONY: all
|
||||
all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6)
|
||||
###################################################
|
||||
# Linker
|
||||
###################################################
|
||||
$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
|
||||
$(LD) $(OBJ_FILE_SA0) \
|
||||
-T $(MEMORY_DEF_SA0) \
|
||||
-o $(OUTPUT_FILE_SA0) \
|
||||
-Map $(FILE_NAME_SA0).map \
|
||||
|
||||
$(objcopy) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
|
||||
$(objcopy) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
|
||||
|
||||
$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
|
||||
$(LD) $(OBJ_FILE_SA6) \
|
||||
-T $(MEMORY_DEF_SA6) \
|
||||
-o $(OUTPUT_FILE_SA6) \
|
||||
-Map $(FILE_NAME_SA6).map \
|
||||
|
||||
$(objcopy) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
|
||||
$(objcopy) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
|
||||
|
||||
###################################################
|
||||
# Compile
|
||||
###################################################
|
||||
|
||||
%.o:../%.c
|
||||
$(CC) -c -I $< -o $@
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
$(CL) *.bin *.map *.srec *.elf *.o
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define RCAR_SA0_SIZE_SMALL (0) /* for RZ/G2E */
|
||||
#define RCAR_SA0_SIZE_NORMAL (1) /* for RZ/G2[HMN] */
|
||||
|
||||
#define BL2_ADDRESS (0xE6304000) /* BL2 start address */
|
||||
|
||||
#if (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL)
|
||||
#define BL2_SIZE (80*1024/4) /* BL2 size is 80KB(0x00005000) */
|
||||
#else /* (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL) */
|
||||
#define BL2_SIZE (170*1024/4) /* BL2 size is 170KB(0x0000AA00) */
|
||||
#endif /* (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL) */
|
||||
|
||||
/* SA0 */
|
||||
/* 0x00000000 */
|
||||
const unsigned int __attribute__ ((section(".sa0_bootrom"))) bootrom_paramA = 0x00000100;
|
||||
/* 0x00000080 (Map Type 3 for eMMC Boot)*/
|
||||
/* 0x000001D4 */
|
||||
const unsigned int __attribute__ ((section(".sa0_bl2dst_addr3"))) bl2dst_addr3 = BL2_ADDRESS;
|
||||
/* 0x000002E4 */
|
||||
const unsigned int __attribute__ ((section(".sa0_bl2dst_size3"))) bl2dst_size3 = BL2_SIZE;
|
||||
/* 0x00000C00 (Map Type 1 for HyperFlash/QSPI Flash Boot)*/
|
||||
/* 0x00000D54 */
|
||||
const unsigned int __attribute__ ((section(".sa0_bl2dst_addr1"))) bl2dst_addr1 = BL2_ADDRESS;
|
||||
/* 0x00000E64 */
|
||||
const unsigned int __attribute__ ((section(".sa0_bl2dst_size1"))) bl2dst_size1 = BL2_SIZE;
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
.rodata : {
|
||||
KEEP(*(.sa0_bootrom))
|
||||
/* Map Type 3 for eMMC Boot */
|
||||
/* A-side IPL content cert "Start Address" */
|
||||
. = 0x000001D4; /* H'00000080 + H'00000154 */
|
||||
KEEP(*(.sa0_bl2dst_addr3))
|
||||
/* A-side IPL content cert "Size" */
|
||||
. = 0x000002E4; /* H'00000080 + H'00000264 */
|
||||
KEEP(*(.sa0_bl2dst_size3))
|
||||
/* Map Type 1 for HyperFlash/QSPI Flash Boot */
|
||||
/* A-side IPL content cert "Start Address" */
|
||||
. = 0x00000D54; /* H'00000C00 + H'00000154 */
|
||||
KEEP(*(.sa0_bl2dst_addr1))
|
||||
/* A-side IPL content cert "Size" */
|
||||
. = 0x00000E64; /* H'00000C00 + H'00000264 */
|
||||
KEEP(*(.sa0_bl2dst_size1))
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define RCAR_SA6_TYPE_QSPIFLASH (0)
|
||||
#define RCAR_SA6_TYPE_EMMC (1)
|
||||
|
||||
#if (RCAR_SA6_TYPE == RCAR_SA6_TYPE_QSPIFLASH)
|
||||
|
||||
/* Number of content cert for Non-secure Target Program(BL33x) */
|
||||
#define RCAR_IMAGE_NUM (0x00000001U)
|
||||
/* Source address on flash for BL31 */
|
||||
#define RCAR_BL31SRC_ADDRESS (0x001C0000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL31_PARTITION (0x00000000U)
|
||||
/* Source address on flash for BL32 */
|
||||
#define RCAR_BL32SRC_ADDRESS (0x00200000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL32_PARTITION (0x00000000U)
|
||||
/* Source address on flash for BL33 */
|
||||
#define RCAR_BL33SRC_ADDRESS (0x00300000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL33_PARTITION (0x00000000U)
|
||||
#define RCAR_BL332SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL332_PARTITION (0x00000000U)
|
||||
#define RCAR_BL333SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL333_PARTITION (0x00000000U)
|
||||
#define RCAR_BL334SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL334_PARTITION (0x00000000U)
|
||||
#define RCAR_BL335SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL335_PARTITION (0x00000000U)
|
||||
#define RCAR_BL336SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL336_PARTITION (0x00000000U)
|
||||
#define RCAR_BL337SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL337_PARTITION (0x00000000U)
|
||||
#define RCAR_BL338SRC_ADDRESS (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL338_PARTITION (0x00000000U)
|
||||
|
||||
#else /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_EMMC */
|
||||
|
||||
/* Number of content cert for Non-secure Target Program(BL33x) */
|
||||
#define RCAR_IMAGE_NUM (0x00000001U)
|
||||
/* Source address on eMMC for BL31 */
|
||||
#define RCAR_BL31SRC_ADDRESS (0x00040000U)
|
||||
/* Source partition on eMMC for BL31 */
|
||||
#define RCAR_BL31_PARTITION (0x00000001U)
|
||||
/* Source address on eMMC for BL32 */
|
||||
#define RCAR_BL32SRC_ADDRESS (0x00200000U)
|
||||
/* Source partition on eMMC for BL32 */
|
||||
#define RCAR_BL32_PARTITION (0x00000001U)
|
||||
/* Source address on eMMC for BL33 */
|
||||
#define RCAR_BL33SRC_ADDRESS (0x00000000U)
|
||||
/* Source partition on eMMC for BL33 */
|
||||
#define RCAR_BL33_PARTITION (0x00000002U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL332SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL332_PARTITION (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL333SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL333_PARTITION (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL334SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL334_PARTITION (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL335SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL335_PARTITION (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL336SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL336_PARTITION (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL337SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL337_PARTITION (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL338SRC_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL338_PARTITION (0x00000000U)
|
||||
|
||||
#endif /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_QSPIFLASH */
|
||||
|
||||
/* Destination address for BL31 */
|
||||
#define RCAR_BL31DST_ADDRESS (0x44000000U)
|
||||
#define RCAR_BL31DST_ADDRESSH (0x00000000U)
|
||||
/* Destination size for BL31 */
|
||||
#define RCAR_BL31DST_SIZE (0x00004000U)
|
||||
/* Destination address for BL32 */
|
||||
#define RCAR_BL32DST_ADDRESS (0x44100000U)
|
||||
#define RCAR_BL32DST_ADDRESSH (0x00000000U)
|
||||
/* Destination size for BL32 */
|
||||
#define RCAR_BL32DST_SIZE (0x00040000U)
|
||||
/* Destination address for BL33 */
|
||||
#define RCAR_BL33DST_ADDRESS (0x50000000U)
|
||||
#define RCAR_BL33DST_ADDRESSH (0x00000000U)
|
||||
/* Destination size for BL33 */
|
||||
#define RCAR_BL33DST_SIZE (0x00040000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL332DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL332DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL332DST_SIZE (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL333DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL333DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL333DST_SIZE (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL334DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL334DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL334DST_SIZE (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL335DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL335DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL335DST_SIZE (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL336DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL336DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL336DST_SIZE (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL337DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL337DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL337DST_SIZE (0x00000000U)
|
||||
/* Reserved */
|
||||
#define RCAR_BL338DST_ADDRESS (0x00000000U)
|
||||
#define RCAR_BL338DST_ADDRESSH (0x00000000U)
|
||||
#define RCAR_BL338DST_SIZE (0x00000000U)
|
||||
|
||||
/* SA6 */
|
||||
const uint64_t __attribute__ ((section(".sa6_image_num")))
|
||||
image_num = RCAR_IMAGE_NUM;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl31src_addr")))
|
||||
bl31src_addr = RCAR_BL31SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl31partition")))
|
||||
bl31partition = RCAR_BL31_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl32src_addr")))
|
||||
bl32src_addr = RCAR_BL32SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl32partition")))
|
||||
bl32partition = RCAR_BL32_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl33src_addr")))
|
||||
bl33src_addr = RCAR_BL33SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl33partition")))
|
||||
bl33partition = RCAR_BL33_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl332src_addr")))
|
||||
bl332src_addr = RCAR_BL332SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl332partition")))
|
||||
bl332partition = RCAR_BL332_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl333src_addr")))
|
||||
bl333src_addr = RCAR_BL333SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl333partition")))
|
||||
bl333partition = RCAR_BL333_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl334src_addr")))
|
||||
bl334src_addr = RCAR_BL334SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl334partition")))
|
||||
bl334partition = RCAR_BL334_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl335src_addr")))
|
||||
bl335src_addr = RCAR_BL335SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl335partition")))
|
||||
bl335partition = RCAR_BL335_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl336src_addr")))
|
||||
bl336src_addr = RCAR_BL336SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl336partition")))
|
||||
bl336partition = RCAR_BL336_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl337src_addr")))
|
||||
bl337src_addr = RCAR_BL337SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl337partition")))
|
||||
bl337partition = RCAR_BL337_PARTITION;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl338src_addr")))
|
||||
bl338src_addr = RCAR_BL338SRC_ADDRESS;
|
||||
const uint64_t __attribute__ ((section(".sa6_bl338partition")))
|
||||
bl338partition = RCAR_BL338_PARTITION;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl31dst_addr")))
|
||||
bl31dst_addr = RCAR_BL31DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl31dst_addrh")))
|
||||
bl31dst_addrh = RCAR_BL31DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl31dst_size")))
|
||||
bl31dst_size = RCAR_BL31DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl32dst_addr")))
|
||||
bl32dst_addr = RCAR_BL32DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl32dst_addrh")))
|
||||
bl32dst_addrh = RCAR_BL32DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl32dst_size")))
|
||||
bl32dst_size = RCAR_BL32DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl33dst_addr")))
|
||||
bl33dst_addr = RCAR_BL33DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl33dst_addrh")))
|
||||
bl33dst_addrh = RCAR_BL33DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl33dst_size")))
|
||||
bl33dst_size = RCAR_BL33DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl332dst_addr")))
|
||||
bl332dst_addr = RCAR_BL332DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl332dst_addrh")))
|
||||
bl332dst_addrh = RCAR_BL332DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl332dst_size")))
|
||||
bl332dst_size = RCAR_BL332DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl333dst_addr")))
|
||||
bl333dst_addr = RCAR_BL333DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl333dst_addrh")))
|
||||
bl333dst_addrh = RCAR_BL333DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl333dst_size")))
|
||||
bl333dst_size = RCAR_BL333DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl334dst_addr")))
|
||||
bl334dst_addr = RCAR_BL334DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl334dst_addrh")))
|
||||
bl334dst_addrh = RCAR_BL334DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl334dst_size")))
|
||||
bl334dst_size = RCAR_BL334DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl335dst_addr")))
|
||||
bl335dst_addr = RCAR_BL335DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl335dst_addrh")))
|
||||
bl335dst_addrh = RCAR_BL335DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl335dst_size")))
|
||||
bl335dst_size = RCAR_BL335DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl336dst_addr")))
|
||||
bl336dst_addr = RCAR_BL336DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl336dst_addrh")))
|
||||
bl336dst_addrh = RCAR_BL336DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl336dst_size")))
|
||||
bl336dst_size = RCAR_BL336DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl337dst_addr")))
|
||||
bl337dst_addr = RCAR_BL337DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl337dst_addrh")))
|
||||
bl337dst_addrh = RCAR_BL337DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl337dst_size")))
|
||||
bl337dst_size = RCAR_BL337DST_SIZE;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl338dst_addr")))
|
||||
bl338dst_addr = RCAR_BL338DST_ADDRESS;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl338dst_addrh")))
|
||||
bl338dst_addrh = RCAR_BL338DST_ADDRESSH;
|
||||
const uint32_t __attribute__ ((section(".sa6_bl338dst_size")))
|
||||
bl338dst_size = RCAR_BL338DST_SIZE;
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
.rodata : {
|
||||
KEEP(*(.sa6_image_num))
|
||||
. = 0x00000008;
|
||||
KEEP(*(.sa6_bl31src_addr))
|
||||
. = 0x00000010;
|
||||
KEEP(*(.sa6_bl31partition))
|
||||
. = 0x00000018;
|
||||
KEEP(*(.sa6_bl32src_addr))
|
||||
. = 0x00000020;
|
||||
KEEP(*(.sa6_bl32partition))
|
||||
. = 0x00000028;
|
||||
KEEP(*(.sa6_bl33src_addr))
|
||||
. = 0x00000030;
|
||||
KEEP(*(.sa6_bl33partition))
|
||||
. = 0x00000038;
|
||||
KEEP(*(.sa6_bl332src_addr))
|
||||
. = 0x00000040;
|
||||
KEEP(*(.sa6_bl332partition))
|
||||
. = 0x00000048;
|
||||
KEEP(*(.sa6_bl333src_addr))
|
||||
. = 0x00000050;
|
||||
KEEP(*(.sa6_bl333partition))
|
||||
. = 0x00000058;
|
||||
KEEP(*(.sa6_bl334src_addr))
|
||||
. = 0x00000060;
|
||||
KEEP(*(.sa6_bl334partition))
|
||||
. = 0x00000068;
|
||||
KEEP(*(.sa6_bl335src_addr))
|
||||
. = 0x00000070;
|
||||
KEEP(*(.sa6_bl335partition))
|
||||
. = 0x00000078;
|
||||
KEEP(*(.sa6_bl336src_addr))
|
||||
. = 0x00000080;
|
||||
KEEP(*(.sa6_bl336partition))
|
||||
. = 0x00000088;
|
||||
KEEP(*(.sa6_bl337src_addr))
|
||||
. = 0x00000090;
|
||||
KEEP(*(.sa6_bl337partition))
|
||||
. = 0x00000098;
|
||||
KEEP(*(.sa6_bl338src_addr))
|
||||
. = 0x000000A0;
|
||||
KEEP(*(.sa6_bl338partition))
|
||||
. = 0x00000554;
|
||||
KEEP(*(.sa6_bl31dst_addr))
|
||||
. = 0x00000558;
|
||||
KEEP(*(.sa6_bl31dst_addrh))
|
||||
. = 0x00000664;
|
||||
KEEP(*(.sa6_bl31dst_size))
|
||||
. = 0x00000D54;
|
||||
KEEP(*(.sa6_bl32dst_addr))
|
||||
. = 0x00000D58;
|
||||
KEEP(*(.sa6_bl32dst_addrh))
|
||||
. = 0x00000E64;
|
||||
KEEP(*(.sa6_bl32dst_size))
|
||||
. = 0x00001554;
|
||||
KEEP(*(.sa6_bl33dst_addr))
|
||||
. = 0x00001558;
|
||||
KEEP(*(.sa6_bl33dst_addrh))
|
||||
. = 0x00001664;
|
||||
KEEP(*(.sa6_bl33dst_size))
|
||||
. = 0x00001D54;
|
||||
KEEP(*(.sa6_bl332dst_addr))
|
||||
. = 0x00001D58;
|
||||
KEEP(*(.sa6_bl332dst_addrh))
|
||||
. = 0x00001E64;
|
||||
KEEP(*(.sa6_bl332dst_size))
|
||||
. = 0x00002554;
|
||||
KEEP(*(.sa6_bl333dst_addr))
|
||||
. = 0x00002558;
|
||||
KEEP(*(.sa6_bl333dst_addrh))
|
||||
. = 0x00002664;
|
||||
KEEP(*(.sa6_bl333dst_size))
|
||||
. = 0x00002D54;
|
||||
KEEP(*(.sa6_bl334dst_addr))
|
||||
. = 0x00002D58;
|
||||
KEEP(*(.sa6_bl334dst_addrh))
|
||||
. = 0x00002E64;
|
||||
KEEP(*(.sa6_bl334dst_size))
|
||||
. = 0x00003554;
|
||||
KEEP(*(.sa6_bl335dst_addr))
|
||||
. = 0x00003558;
|
||||
KEEP(*(.sa6_bl335dst_addrh))
|
||||
. = 0x00003664;
|
||||
KEEP(*(.sa6_bl335dst_size))
|
||||
. = 0x00003D54;
|
||||
KEEP(*(.sa6_bl336dst_addr))
|
||||
. = 0x00003D58;
|
||||
KEEP(*(.sa6_bl336dst_addrh))
|
||||
. = 0x00003E64;
|
||||
KEEP(*(.sa6_bl336dst_size))
|
||||
. = 0x00004554;
|
||||
KEEP(*(.sa6_bl337dst_addr))
|
||||
. = 0x00004558;
|
||||
KEEP(*(.sa6_bl337dst_addrh))
|
||||
. = 0x00004664;
|
||||
KEEP(*(.sa6_bl337dst_size))
|
||||
. = 0x00004D54;
|
||||
KEEP(*(.sa6_bl338dst_addr))
|
||||
. = 0x00004D58;
|
||||
KEEP(*(.sa6_bl338dst_addrh))
|
||||
. = 0x00004E64;
|
||||
KEEP(*(.sa6_bl338dst_size))
|
||||
}
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue