Merge changes I19e4e7f5,I226b6e33 into integration

* changes:
  marvell: uart: a3720: Fix macro name for 6th bit of Status Register
  marvell: uart: a3720: Implement console_a3700_core_getc
This commit is contained in:
Madhukar Pappireddy 2021-01-20 15:41:26 +00:00 committed by TrustedFirmware Code Review
commit 3adf6012f5
2 changed files with 20 additions and 10 deletions

View File

@ -60,14 +60,14 @@ func console_a3700_core_init
str w3, [x0, #UART_POSSR_REG]
/*
* Wait for the TX FIFO to be empty. If wait for 20ms, the TX FIFO is
* Wait for the TX (THR and TSR) to be empty. If wait for 20ms, the TX FIFO is
* still not empty, TX FIFO will reset by all means.
*/
mov w1, #20 /* max time out 20ms */
2:
/* Check whether TX FIFO is empty */
/* Check whether TX (THR and TSR) is empty */
ldr w3, [x0, #UART_STATUS_REG]
and w3, w3, #UARTLSR_TXFIFOEMPTY
and w3, w3, #UARTLSR_TXEMPTY
cmp w3, #0
b.ne 4f
@ -196,14 +196,23 @@ endfunc console_a3700_putc
* int console_a3700_core_getc(void)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 on error.
* or -1 if no character is available.
* In : w0 - console base address
* Out : return -1 on error else return character.
* Out : w0 - character if available, else -1
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_a3700_core_getc
mov w0, #-1
/* Check if there is a pending character */
ldr w1, [x0, #UART_STATUS_REG]
and w1, w1, #UARTLSR_RXRDY
cmp w1, #UARTLSR_RXRDY
b.ne getc_no_char
ldr w0, [x0, #UART_RX_REG]
and w0, w0, #0xff
ret
getc_no_char:
mov w0, #ERROR_NO_PENDING_CHAR
ret
endfunc console_a3700_core_getc
@ -232,10 +241,10 @@ endfunc console_a3700_getc
* ---------------------------------------------
*/
func console_a3700_core_flush
/* Wait for the TX FIFO to be empty */
/* Wait for the TX (THR and TSR) to be empty */
1: ldr w1, [x0, #UART_STATUS_REG]
and w1, w1, #UARTLSR_TXFIFOEMPTY
cmp w1, #UARTLSR_TXFIFOEMPTY
and w1, w1, #UARTLSR_TXEMPTY
cmp w1, #UARTLSR_TXEMPTY
b.ne 1b
ret
endfunc console_a3700_core_flush

View File

@ -48,11 +48,12 @@
/* Line Status Register bits */
#define UARTLSR_TXFIFOFULL (1 << 11) /* Tx Fifo Full */
#define UARTLSR_TXEMPTY (1 << 6) /* Tx Empty */
#define UARTLSR_RXRDY (1 << 4) /* Rx Ready */
/* UART Control Register bits */
#define UART_CTRL_RXFIFO_RESET (1 << 14)
#define UART_CTRL_TXFIFO_RESET (1 << 15)
#define UARTLSR_TXFIFOEMPTY (1 << 6)
#ifndef __ASSEMBLER__