Merge pull request #1783 from thloh85-intel/integration_v2
plat: intel: Add BL2 support for Stratix 10 SoC
This commit is contained in:
Antonio Niño Díaz
GitHub
commit
6ce3034688
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@ -93,6 +93,12 @@ HiSilicon Poplar platform port
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:F: docs/plat/poplar.rst
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:F: plat/hisilicon/poplar/
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Intel SocFPGA platform ports
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----------------------------
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:M: Tien Hock Loh <tien.hock.loh@intel.com>
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:G: `thloh85-intel`
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:F: plat/intel/soc
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MediaTek platform ports
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-----------------------
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:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com>
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@ -0,0 +1,129 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl platform_is_primary_cpu
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl plat_get_my_entrypoint
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.globl stratix10_sec_entry
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.globl cpuid_release
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Wait until the it gets reset signal from rstmgr gets populated */
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poll_mailbox:
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wfi
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adr x0, stratix10_sec_entry
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ldr x1, [x0]
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adr x2, cpuid_release
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ldr x3, [x2]
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mrs x4, mpidr_el1
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and x4, x4, #0xff
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cmp x3, x4
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b.ne poll_mailbox
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br x1
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endfunc plat_secondary_cold_boot_setup
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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b platform_is_primary_cpu
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endfunc plat_is_my_cpu_primary
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_my_core_pos
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func plat_get_my_entrypoint
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adr x1,stratix10_sec_entry
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_UART0_BASE
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mov_imm x1, PLAT_UART_CLOCK
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mov_imm x2, PLAT_BAUDRATE
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b console_16550_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_UART0_BASE
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b console_16550_core_putc
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov_imm x0, CRASH_CONSOLE_BASE
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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.data
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.align 3
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stratix10_sec_entry:
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.quad 0
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cpuid_release:
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.quad 0
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@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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unsigned int plat_get_syscnt_freq2(void)
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{
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return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return PLAT_NS_IMAGE_OFFSET;
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}
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/******************************************************************************
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* Gets SPSR for BL32 entry
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*****************************************************************************/
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uint32_t plat_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/******************************************************************************
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* Gets SPSR for BL33 entry
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*****************************************************************************/
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uint32_t plat_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __S10_PRIVATE_H__
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#define __S10_PRIVATE_H__
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#define S10_MMC_REG_BASE 0xff808000
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#define EMMC_DESC_SIZE (1<<20)
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#define EMMC_INIT_PARAMS(base) \
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{ .bus_width = MMC_BUS_WIDTH_4, \
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.clk_rate = 50000000, \
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.desc_base = (base), \
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.desc_size = EMMC_DESC_SIZE, \
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.flags = 0, \
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.reg_base = S10_MMC_REG_BASE, \
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\
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}
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typedef enum {
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BOOT_SOURCE_FPGA = 0,
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BOOT_SOURCE_SDMMC,
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BOOT_SOURCE_NAND,
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BOOT_SOURCE_RSVD,
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BOOT_SOURCE_QSPI,
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} boot_source_type;
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void enable_nonsecure_access(void);
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void stratix10_io_setup(void);
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#endif
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@ -0,0 +1,96 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef SCP_BL2_BASE
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/* Fill SCP_BL2 related information if it exists */
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{
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = SCP_BL2_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* SCP_BL2_BASE */
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#ifdef EL3_PAYLOAD_BASE
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/* Fill EL3 payload related information (BL31 is EL3 payload)*/
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = EL3_PAYLOAD_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#else /* EL3_PAYLOAD_BASE */
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/* Fill BL31 related information */
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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#endif /* EL3_PAYLOAD_BASE */
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
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.image_info.image_max_size =
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0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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@ -0,0 +1,162 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/console.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <errno.h>
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#include <drivers/io/io_storage.h>
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#include <common/image_decompress.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <platform_private.h>
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#include <drivers/synopsys/dw_mmc.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "s10_memory_controller.h"
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#include "s10_reset_manager.h"
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#include "s10_clock_manager.h"
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#include "s10_handoff.h"
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#include "s10_pinmux.h"
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#include "aarch64/stratix10_private.h"
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const mmap_region_t plat_stratix10_mmap[] = {
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MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
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{0},
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};
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boot_source_type boot_source;
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void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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u_register_t x2, u_register_t x4)
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{
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static console_16550_t console;
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handoff reverse_handoff_ptr;
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generic_delay_timer_init();
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if (s10_get_handoff(&reverse_handoff_ptr))
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return;
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config_pinmux(&reverse_handoff_ptr);
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boot_source = reverse_handoff_ptr.boot_source;
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config_clkmgr_handoff(&reverse_handoff_ptr);
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enable_nonsecure_access();
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deassert_peripheral_reset();
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config_hps_hs_before_warm_reset();
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console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
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&console);
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plat_delay_timer_init();
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init_hard_memory_controller();
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}
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void bl2_el3_plat_arch_setup(void)
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{
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struct mmc_device_info info;
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const mmap_region_t bl_regions[] = {
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MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE),
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MAP_REGION_FLAT(BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE),
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#if USE_COHERENT_MEM_BAR
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MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE),
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#endif
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{0},
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};
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setup_page_tables(bl_regions, plat_stratix10_mmap);
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enable_mmu_el3(0);
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/* ECC Scrubbing */
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memset(0, DRAM_BASE, DRAM_SIZE);
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dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
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||||
|
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info.mmc_dev_type = MMC_IS_SD;
|
||||
|
||||
switch (boot_source) {
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case BOOT_SOURCE_SDMMC:
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dw_mmc_init(¶ms, &info);
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stratix10_io_setup();
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||||
break;
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default:
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ERROR("Unsupported boot source\n");
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panic();
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||||
break;
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||||
}
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||||
}
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||||
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||||
uint32_t get_spsr_for_bl33_entry(void)
|
||||
{
|
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unsigned long el_status;
|
||||
unsigned int mode;
|
||||
uint32_t spsr;
|
||||
|
||||
/* Figure out what mode we enter the non-secure world in */
|
||||
el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
|
||||
el_status &= ID_AA64PFR0_ELX_MASK;
|
||||
|
||||
mode = (el_status) ? MODE_EL2 : MODE_EL1;
|
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|
||||
/*
|
||||
* TODO: Consider the possibility of specifying the SPSR in
|
||||
* the FIP ToC and allowing the platform to have a say as
|
||||
* well.
|
||||
*/
|
||||
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
|
||||
return spsr;
|
||||
}
|
||||
|
||||
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
||||
|
||||
switch (image_id) {
|
||||
case BL33_IMAGE_ID:
|
||||
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
|
||||
bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Perform any BL3-1 platform setup code
|
||||
******************************************************************************/
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_MACROS_S__
|
||||
#define __PLAT_MACROS_S__
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below required platform porting macro
|
||||
* prints out relevant platform registers
|
||||
* whenever an unhandled exception is taken in
|
||||
* BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
mov_imm x17, PLAT_GICC_BASE
|
||||
mov_imm x16, PLAT_GICD_BASE
|
||||
arm_print_gic_regs
|
||||
.endm
|
||||
|
||||
#endif /* __PLAT_MACROS_S__ */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_PRIVATE_H__
|
||||
#define __PLATFORM_PRIVATE_H__
|
||||
#include <common/bl_common.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Function and variable prototypes
|
||||
******************************************************************************/
|
||||
void plat_configure_mmu_el3(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
|
||||
|
||||
void plat_configure_mmu_el1(unsigned long total_base,
|
||||
unsigned long total_size,
|
||||
unsigned long ro_start,
|
||||
unsigned long ro_limit,
|
||||
unsigned long coh_start,
|
||||
unsigned long coh_limit);
|
||||
|
||||
void plat_gic_driver_init(void);
|
||||
|
||||
void plat_arm_gic_init(void);
|
||||
|
||||
void plat_delay_timer_init(void);
|
||||
|
||||
unsigned long plat_get_ns_image_entrypoint(void);
|
||||
|
||||
uint32_t plat_get_spsr_for_bl32_entry(void);
|
||||
|
||||
uint32_t plat_get_spsr_for_bl33_entry(void);
|
||||
|
||||
#endif /* __PLATFORM_PRIVATE_H__ */
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __CLOCKMANAGER_H__
|
||||
#define __CLOCKMANAGER_H__
|
||||
|
||||
#include "s10_handoff.h"
|
||||
|
||||
#define ALT_CLKMGR 0xffd10000
|
||||
|
||||
#define ALT_CLKMGR_CTRL 0x0
|
||||
#define ALT_CLKMGR_STAT 0x4
|
||||
#define ALT_CLKMGR_INTRCLR 0x14
|
||||
#define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
|
||||
#define ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
|
||||
|
||||
#define ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001
|
||||
#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
|
||||
#define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0)
|
||||
#define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8)
|
||||
#define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9)
|
||||
|
||||
#define ALT_CLKMGR_MAINPLL 0xffd10030
|
||||
#define ALT_CLKMGR_MAINPLL_EN 0x0
|
||||
#define ALT_CLKMGR_MAINPLL_BYPASS 0xc
|
||||
#define ALT_CLKMGR_MAINPLL_MPUCLK 0x18
|
||||
#define ALT_CLKMGR_MAINPLL_NOCCLK 0x1c
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR2CLK 0x20
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR3CLK 0x24
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR4CLK 0x28
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR5CLK 0x2c
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR6CLK 0x30
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR7CLK 0x34
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR8CLK 0x38
|
||||
#define ALT_CLKMGR_MAINPLL_CNTR9CLK 0x3c
|
||||
#define ALT_CLKMGR_MAINPLL_NOCDIV 0x40
|
||||
#define ALT_CLKMGR_MAINPLL_PLLGLOB 0x44
|
||||
#define ALT_CLKMGR_MAINPLL_FDBCK 0x48
|
||||
#define ALT_CLKMGR_MAINPLL_PLLC0 0x54
|
||||
#define ALT_CLKMGR_MAINPLL_PLLC1 0x58
|
||||
#define ALT_CLKMGR_MAINPLL_VCOCALIB 0x5c
|
||||
#define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff
|
||||
#define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24)
|
||||
#define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001
|
||||
#define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
|
||||
#define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002
|
||||
#define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff)
|
||||
#define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00)
|
||||
|
||||
#define ALT_CLKMGR_PERPLL 0xffd100a4
|
||||
#define ALT_CLKMGR_PERPLL_EN 0x0
|
||||
#define ALT_CLKMGR_PERPLL_BYPASS 0xc
|
||||
#define ALT_CLKMGR_PERPLL_CNTR2CLK 0x18
|
||||
#define ALT_CLKMGR_PERPLL_CNTR3CLK 0x1c
|
||||
#define ALT_CLKMGR_PERPLL_CNTR4CLK 0x20
|
||||
#define ALT_CLKMGR_PERPLL_CNTR5CLK 0x24
|
||||
#define ALT_CLKMGR_PERPLL_CNTR6CLK 0x28
|
||||
#define ALT_CLKMGR_PERPLL_CNTR7CLK 0x2c
|
||||
#define ALT_CLKMGR_PERPLL_CNTR8CLK 0x30
|
||||
#define ALT_CLKMGR_PERPLL_CNTR9CLK 0x34
|
||||
#define ALT_CLKMGR_PERPLL_GPIODIV 0x3c
|
||||
#define ALT_CLKMGR_PERPLL_EMACCTL 0x38
|
||||
#define ALT_CLKMGR_PERPLL_PLLGLOB 0x40
|
||||
#define ALT_CLKMGR_PERPLL_FDBCK 0x44
|
||||
#define ALT_CLKMGR_PERPLL_PLLC0 0x50
|
||||
#define ALT_CLKMGR_PERPLL_PLLC1 0x54
|
||||
#define ALT_CLKMGR_PERPLL_EN_RESET 0x00000fff
|
||||
#define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24)
|
||||
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
|
||||
#define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
|
||||
#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
|
||||
#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET(x) (((x) << 8) & 0x00003f00)
|
||||
#define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
|
||||
#define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff)
|
||||
#define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00)
|
||||
#define ALT_CLKMGR_PERPLL_VCOCALIB 0x58
|
||||
|
||||
void config_clkmgr_handoff(handoff *hoff_ptr);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _HANDOFF_H_
|
||||
#define _HANDOFF_H_
|
||||
|
||||
#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
|
||||
#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
|
||||
#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
|
||||
#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
|
||||
#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
|
||||
#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
|
||||
#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
|
||||
|
||||
typedef struct handoff_t {
|
||||
/* header */
|
||||
uint32_t header_magic;
|
||||
uint32_t header_device;
|
||||
uint32_t _pad_0x08_0x10[2];
|
||||
|
||||
/* pinmux configuration - select */
|
||||
uint32_t pinmux_sel_magic;
|
||||
uint32_t pinmux_sel_length;
|
||||
uint32_t _pad_0x18_0x20[2];
|
||||
uint32_t pinmux_sel_array[96]; /* offset, value */
|
||||
|
||||
/* pinmux configuration - io control */
|
||||
uint32_t pinmux_io_magic;
|
||||
uint32_t pinmux_io_length;
|
||||
uint32_t _pad_0x1a8_0x1b0[2];
|
||||
uint32_t pinmux_io_array[96]; /* offset, value */
|
||||
|
||||
/* pinmux configuration - use fpga switch */
|
||||
uint32_t pinmux_fpga_magic;
|
||||
uint32_t pinmux_fpga_length;
|
||||
uint32_t _pad_0x338_0x340[2];
|
||||
uint32_t pinmux_fpga_array[42]; /* offset, value */
|
||||
uint32_t _pad_0x3e8_0x3f0[2];
|
||||
|
||||
/* pinmux configuration - io delay */
|
||||
uint32_t pinmux_delay_magic;
|
||||
uint32_t pinmux_delay_length;
|
||||
uint32_t _pad_0x3f8_0x400[2];
|
||||
uint32_t pinmux_iodelay_array[96]; /* offset, value */
|
||||
|
||||
/* clock configuration */
|
||||
uint32_t clock_magic;
|
||||
uint32_t clock_length;
|
||||
uint32_t _pad_0x588_0x590[2];
|
||||
uint32_t main_pll_mpuclk;
|
||||
uint32_t main_pll_nocclk;
|
||||
uint32_t main_pll_cntr2clk;
|
||||
uint32_t main_pll_cntr3clk;
|
||||
uint32_t main_pll_cntr4clk;
|
||||
uint32_t main_pll_cntr5clk;
|
||||
uint32_t main_pll_cntr6clk;
|
||||
uint32_t main_pll_cntr7clk;
|
||||
uint32_t main_pll_cntr8clk;
|
||||
uint32_t main_pll_cntr9clk;
|
||||
uint32_t main_pll_nocdiv;
|
||||
uint32_t main_pll_pllglob;
|
||||
uint32_t main_pll_fdbck;
|
||||
uint32_t main_pll_pllc0;
|
||||
uint32_t main_pll_pllc1;
|
||||
uint32_t _pad_0x5cc_0x5d0[1];
|
||||
uint32_t per_pll_cntr2clk;
|
||||
uint32_t per_pll_cntr3clk;
|
||||
uint32_t per_pll_cntr4clk;
|
||||
uint32_t per_pll_cntr5clk;
|
||||
uint32_t per_pll_cntr6clk;
|
||||
uint32_t per_pll_cntr7clk;
|
||||
uint32_t per_pll_cntr8clk;
|
||||
uint32_t per_pll_cntr9clk;
|
||||
uint32_t per_pll_emacctl;
|
||||
uint32_t per_pll_gpiodiv;
|
||||
uint32_t per_pll_pllglob;
|
||||
uint32_t per_pll_fdbck;
|
||||
uint32_t per_pll_pllc0;
|
||||
uint32_t per_pll_pllc1;
|
||||
uint32_t hps_osc_clk_h;
|
||||
uint32_t fpga_clk_hz;
|
||||
|
||||
/* misc configuration */
|
||||
uint32_t misc_magic;
|
||||
uint32_t misc_length;
|
||||
uint32_t _pad_0x618_0x620[2];
|
||||
uint32_t boot_source;
|
||||
} handoff;
|
||||
|
||||
int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
|
||||
int s10_get_handoff(handoff *hoff_ptr);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __S10_MEMORYCONTROLLER_H__
|
||||
#define __S10_MEMORYCONTROLLER_H__
|
||||
|
||||
#define S10_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8
|
||||
#define S10_MPFE_IOHMC_CTRLCFG0 0xf8010028
|
||||
#define S10_MPFE_IOHMC_CTRLCFG1 0xf801002c
|
||||
#define S10_MPFE_IOHMC_DRAMADDRW 0xf80100a8
|
||||
#define S10_MPFE_IOHMC_DRAMTIMING0 0xf8010050
|
||||
#define S10_MPFE_IOHMC_CALTIMING0 0xf801007c
|
||||
#define S10_MPFE_IOHMC_CALTIMING1 0xf8010080
|
||||
#define S10_MPFE_IOHMC_CALTIMING2 0xf8010084
|
||||
#define S10_MPFE_IOHMC_CALTIMING3 0xf8010088
|
||||
#define S10_MPFE_IOHMC_CALTIMING4 0xf801008c
|
||||
#define S10_MPFE_IOHMC_CALTIMING9 0xf80100a0
|
||||
#define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0)
|
||||
#define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \
|
||||
(((value) & 0x00000060) >> 5)
|
||||
|
||||
#define S10_RSTMGR_BRGMODRST 0xffd1102c
|
||||
#define S10_RSTMGR_BRGMODRST_DDRSCH 0x00000040
|
||||
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
|
||||
#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
|
||||
#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff
|
||||
#define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214
|
||||
|
||||
|
||||
#define S10_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c
|
||||
|
||||
#define S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110
|
||||
|
||||
#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
|
||||
#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
|
||||
#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
|
||||
#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
|
||||
#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
|
||||
|
||||
#define S10_MPFE_DDR(x) (0xf8000000 + x)
|
||||
#define S10_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c
|
||||
#define S10_MPFE_DDR_MAIN_SCHED 0xf8000400
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f)
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2
|
||||
#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4
|
||||
|
||||
#define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x))
|
||||
#define S10_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210
|
||||
#define S10_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008
|
||||
#define HMC_ADP_DDRIOCTRL 0x8
|
||||
#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
|
||||
#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9)
|
||||
#define ADP_DRAMADDRWIDTH 0xe0
|
||||
|
||||
#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18)
|
||||
#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
|
||||
#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0)
|
||||
#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
|
||||
|
||||
/* timing 2 */
|
||||
#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6)
|
||||
#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24)
|
||||
#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18)
|
||||
#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6)
|
||||
|
||||
/* timing 3 */
|
||||
#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12)
|
||||
#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6)
|
||||
|
||||
/* timing 4 */
|
||||
#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6)
|
||||
|
||||
#define DDRTIMING_BWRATIO_OFST 31
|
||||
#define DDRTIMING_WRTORD_OFST 26
|
||||
#define DDRTIMING_RDTOWR_OFST 21
|
||||
#define DDRTIMING_BURSTLEN_OFST 18
|
||||
#define DDRTIMING_WRTOMISS_OFST 12
|
||||
#define DDRTIMING_RDTOMISS_OFST 6
|
||||
#define DDRTIMING_ACTTOACT_OFST 0
|
||||
|
||||
#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
|
||||
|
||||
#define DDRMODE_AUTOPRECHARGE_OFST 1
|
||||
#define DDRMODE_BWRATIOEXTENDED_OFST 0
|
||||
|
||||
|
||||
#define S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x0000007f) >> 0)
|
||||
#define S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0000000f) >> 0)
|
||||
|
||||
#define S10_CCU_CPU0_MPRT_DDR 0xf7004400
|
||||
#define S10_CCU_CPU0_MPRT_MEM0 0xf70045c0
|
||||
#define S10_CCU_CPU0_MPRT_MEM1A 0xf70045e0
|
||||
#define S10_CCU_CPU0_MPRT_MEM1B 0xf7004600
|
||||
#define S10_CCU_CPU0_MPRT_MEM1C 0xf7004620
|
||||
#define S10_CCU_CPU0_MPRT_MEM1D 0xf7004640
|
||||
#define S10_CCU_CPU0_MPRT_MEM1E 0xf7004660
|
||||
#define S10_CCU_IOM_MPRT_MEM0 0xf7018560
|
||||
#define S10_CCU_IOM_MPRT_MEM1A 0xf7018580
|
||||
#define S10_CCU_IOM_MPRT_MEM1B 0xf70185a0
|
||||
#define S10_CCU_IOM_MPRT_MEM1C 0xf70185c0
|
||||
#define S10_CCU_IOM_MPRT_MEM1D 0xf70185e0
|
||||
#define S10_CCU_IOM_MPRT_MEM1E 0xf7018600
|
||||
|
||||
#define S10_NOC_FW_DDR_SCR 0xf8020100
|
||||
#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802011c
|
||||
#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020118
|
||||
#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802019c
|
||||
#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020198
|
||||
|
||||
#define S10_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020100
|
||||
#define S10_CCU_NOC_DI_SET_MSK 0x10
|
||||
|
||||
#define S10_SYSMGR_CORE_HMC_CLK 0xffd120b4
|
||||
#define S10_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001
|
||||
|
||||
#define S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0x0000ffff) >> 0)
|
||||
#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
|
||||
#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0
|
||||
#define S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f
|
||||
#define S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7
|
||||
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001
|
||||
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
|
||||
#define S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100
|
||||
#define S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x00000001) >> 0)
|
||||
|
||||
|
||||
#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
|
||||
#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
|
||||
#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
|
||||
#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
|
||||
#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
|
||||
#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
|
||||
|
||||
#define S10_SDRAM_0_LB_ADDR 0x0
|
||||
|
||||
int init_hard_memory_controller(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define AXI_AP (1<<0)
|
||||
#define FPGA2SOC (1<<16)
|
||||
#define MPU (1<<24)
|
||||
#define S10_NOC_PER_SCR_NAND 0xffd21000
|
||||
#define S10_NOC_PER_SCR_NAND_DATA 0xffd21004
|
||||
#define S10_NOC_PER_SCR_USB0 0xffd2100c
|
||||
#define S10_NOC_PER_SCR_USB1 0xffd21010
|
||||
#define S10_NOC_PER_SCR_SPI_M0 0xffd2101c
|
||||
#define S10_NOC_PER_SCR_SPI_M1 0xffd21020
|
||||
#define S10_NOC_PER_SCR_SPI_S0 0xffd21024
|
||||
#define S10_NOC_PER_SCR_SPI_S1 0xffd21028
|
||||
#define S10_NOC_PER_SCR_EMAC0 0xffd2102c
|
||||
#define S10_NOC_PER_SCR_EMAC1 0xffd21030
|
||||
#define S10_NOC_PER_SCR_EMAC2 0xffd21034
|
||||
#define S10_NOC_PER_SCR_SDMMC 0xffd21040
|
||||
#define S10_NOC_PER_SCR_GPIO0 0xffd21044
|
||||
#define S10_NOC_PER_SCR_GPIO1 0xffd21048
|
||||
#define S10_NOC_PER_SCR_I2C0 0xffd21050
|
||||
#define S10_NOC_PER_SCR_I2C1 0xffd21058
|
||||
#define S10_NOC_PER_SCR_I2C2 0xffd2105c
|
||||
#define S10_NOC_PER_SCR_I2C3 0xffd21060
|
||||
#define S10_NOC_PER_SCR_SP_TIMER0 0xffd21064
|
||||
#define S10_NOC_PER_SCR_SP_TIMER1 0xffd21068
|
||||
#define S10_NOC_PER_SCR_UART0 0xffd2106c
|
||||
#define S10_NOC_PER_SCR_UART1 0xffd21070
|
||||
|
||||
|
||||
#define S10_NOC_SYS_SCR_DMA_ECC 0xffd21108
|
||||
#define S10_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c
|
||||
#define S10_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110
|
||||
#define S10_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114
|
||||
#define S10_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118
|
||||
#define S10_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c
|
||||
#define S10_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120
|
||||
#define S10_NOC_SYS_SCR_NAND_ECC 0xffd2112c
|
||||
#define S10_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130
|
||||
#define S10_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134
|
||||
#define S10_NOC_SYS_SCR_OCRAM_ECC 0xffd21138
|
||||
#define S10_NOC_SYS_SCR_SDMMC_ECC 0xffd21140
|
||||
#define S10_NOC_SYS_SCR_USB0_ECC 0xffd21144
|
||||
#define S10_NOC_SYS_SCR_USB1_ECC 0xffd21148
|
||||
#define S10_NOC_SYS_SCR_CLK_MGR 0xffd2114c
|
||||
#define S10_NOC_SYS_SCR_IO_MGR 0xffd21154
|
||||
#define S10_NOC_SYS_SCR_RST_MGR 0xffd21158
|
||||
#define S10_NOC_SYS_SCR_SYS_MGR 0xffd2115c
|
||||
#define S10_NOC_SYS_SCR_OSC0_TIMER 0xffd21160
|
||||
#define S10_NOC_SYS_SCR_OSC1_TIMER 0xffd21164
|
||||
#define S10_NOC_SYS_SCR_WATCHDOG0 0xffd21168
|
||||
#define S10_NOC_SYS_SCR_WATCHDOG1 0xffd2116c
|
||||
#define S10_NOC_SYS_SCR_WATCHDOG2 0xffd21170
|
||||
#define S10_NOC_SYS_SCR_WATCHDOG3 0xffd21174
|
||||
#define S10_NOC_SYS_SCR_DAP 0xffd21178
|
||||
#define S10_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190
|
||||
#define S10_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194
|
||||
|
||||
#define S10_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688
|
||||
#define S10_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __S10_PINMUX_H__
|
||||
#define __S10_PINMUX_H__
|
||||
|
||||
#define S10_PINMUX_PIN0SEL 0xffd13000
|
||||
#define S10_PINMUX_IO0CTRL 0xffd13130
|
||||
#define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300
|
||||
#define S10_PINMUX_IO0_DELAY 0xffd13400
|
||||
|
||||
#include "s10_handoff.h"
|
||||
|
||||
void config_pinmux(handoff *handoff);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __S10_RESETMANAGER_H__
|
||||
#define __S10_RESETMANAGER_H__
|
||||
|
||||
#define S10_RSTMGR_PER0MODRST 0xffd11024
|
||||
#define S10_RSTMGR_PER1MODRST 0xffd11028
|
||||
#define S10_RSTMGR_HDSKEN 0xffd11010
|
||||
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC0OCP 0x00000100
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC1OCP 0x00000200
|
||||
#define S10_RSTMGR_PER0MODRST_DMAOCP 0x00200000
|
||||
#define S10_RSTMGR_PER0MODRST_DMA 0x00010000
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC0 0x00000001
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC1 0x00000002
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC2OCP 0x00000400
|
||||
#define S10_RSTMGR_PER0MODRST_EMAC2 0x00000004
|
||||
#define S10_RSTMGR_PER0MODRST_EMACPTP 0x00400000
|
||||
#define S10_RSTMGR_PER0MODRST_NANDOCP 0x00002000
|
||||
#define S10_RSTMGR_PER0MODRST_NAND 0x00000020
|
||||
#define S10_RSTMGR_PER0MODRST_SDMMCOCP 0x00008000
|
||||
#define S10_RSTMGR_PER0MODRST_SDMMC 0x00000080
|
||||
#define S10_RSTMGR_PER0MODRST_SPIM0 0x00020000
|
||||
#define S10_RSTMGR_PER0MODRST_SPIM1 0x00040000
|
||||
#define S10_RSTMGR_PER0MODRST_SPIS0 0x00080000
|
||||
#define S10_RSTMGR_PER0MODRST_SPIS1 0x00100000
|
||||
#define S10_RSTMGR_PER0MODRST_USB0OCP 0x00000800
|
||||
#define S10_RSTMGR_PER0MODRST_USB0 0x00000008
|
||||
#define S10_RSTMGR_PER0MODRST_USB1OCP 0x00001000
|
||||
#define S10_RSTMGR_PER0MODRST_USB1 0x00000010
|
||||
|
||||
#define S10_RSTMGR_PER1MODRST_WATCHDOG0 0x1
|
||||
#define S10_RSTMGR_PER1MODRST_WATCHDOG1 0x2
|
||||
#define S10_RSTMGR_PER1MODRST_WATCHDOG2 0x4
|
||||
#define S10_RSTMGR_PER1MODRST_WATCHDOG3 0x8
|
||||
#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
|
||||
#define S10_RSTMGR_PER1MODRST_GPIO0 0x01000000
|
||||
#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
|
||||
#define S10_RSTMGR_PER1MODRST_GPIO1 0x02000000
|
||||
#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
|
||||
#define S10_RSTMGR_PER1MODRST_I2C0 0x00000100
|
||||
#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
|
||||
#define S10_RSTMGR_PER1MODRST_I2C1 0x00000200
|
||||
#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
|
||||
#define S10_RSTMGR_PER1MODRST_I2C2 0x00000400
|
||||
#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
|
||||
#define S10_RSTMGR_PER1MODRST_I2C3 0x00000800
|
||||
#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
|
||||
#define S10_RSTMGR_PER1MODRST_I2C4 0x00001000
|
||||
#define S10_RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010
|
||||
#define S10_RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020
|
||||
#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
|
||||
#define S10_RSTMGR_PER1MODRST_SPTIMER0 0x00000040
|
||||
#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
|
||||
#define S10_RSTMGR_PER1MODRST_SPTIMER1 0x00000080
|
||||
#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
|
||||
#define S10_RSTMGR_PER1MODRST_UART0 0x00010000
|
||||
#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
|
||||
#define S10_RSTMGR_PER1MODRST_UART1 0x00020000
|
||||
#define S10_RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000
|
||||
#define S10_RSTMGR_HDSKEN_ETRSTALLEN 0x00000008
|
||||
#define S10_RSTMGR_HDSKEN_FPGAHSEN 0x00000004
|
||||
#define S10_RSTMGR_HDSKEN_L2FLUSHEN 0x00000100
|
||||
#define S10_RSTMGR_HDSKEN_L3NOC_DBG 0x00010000
|
||||
|
||||
#define S10_RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF0 0x01000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF1 0x02000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF2 0x04000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF3 0x08000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF4 0x10000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF5 0x20000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF6 0x40000000
|
||||
#define S10_RSTMGR_PER0MODRST_DMAIF7 0x80000000
|
||||
|
||||
void deassert_peripheral_reset(void);
|
||||
void config_hps_hs_before_warm_reset(void);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
|
||||
#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
|
||||
#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
|
||||
#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
|
||||
#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
|
||||
#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
|
||||
#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
|
||||
#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
|
||||
#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
|
||||
#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
|
||||
#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
|
||||
#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
|
||||
#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
|
||||
#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
|
||||
#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
|
||||
#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
|
||||
#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
|
||||
#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
|
||||
#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
|
||||
#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
|
||||
#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
|
||||
#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
|
||||
#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070
|
||||
|
||||
#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
|
||||
#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
|
||||
#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
|
||||
#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
|
||||
#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
|
||||
#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
|
||||
#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
|
||||
#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
|
||||
#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
|
||||
#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
|
||||
#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
|
||||
#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
|
||||
#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
|
||||
#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
|
||||
#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
|
||||
#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
|
||||
#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
|
||||
#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
|
||||
#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
|
||||
#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
|
||||
#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
|
||||
#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
|
||||
#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
|
||||
#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
|
||||
#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
|
||||
#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
|
||||
#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
|
||||
|
||||
#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
|
||||
#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
|
||||
|
||||
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
|
||||
|
||||
void enable_nonsecure_access(void);
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#define S10_GLOBAL_TIMER 0xffd01000
|
||||
#define S10_GLOBAL_TIMER_EN 0x3
|
||||
|
||||
/********************************************************************
|
||||
* The timer delay function
|
||||
********************************************************************/
|
||||
static uint32_t plat_get_timer_value(void)
|
||||
{
|
||||
/*
|
||||
* Generic delay timer implementation expects the timer to be a down
|
||||
* counter. We apply bitwise NOT operator to the tick values returned
|
||||
* by read_cntpct_el0() to simulate the down counter. The value is
|
||||
* clipped from 64 to 32 bits.
|
||||
*/
|
||||
return (uint32_t)(~read_cntpct_el0());
|
||||
}
|
||||
|
||||
static const timer_ops_t plat_timer_ops = {
|
||||
.get_timer_value = plat_get_timer_value,
|
||||
.clk_mult = 1,
|
||||
.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
|
||||
};
|
||||
|
||||
void plat_delay_timer_init(void)
|
||||
{
|
||||
timer_init(&plat_timer_ops);
|
||||
mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN);
|
||||
}
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/mmc.h>
|
||||
#include <tools_share/firmware_image_package.h>
|
||||
#include <drivers/io/io_block.h>
|
||||
#include <drivers/io/io_driver.h>
|
||||
#include <drivers/io/io_fip.h>
|
||||
#include <drivers/io/io_memmap.h>
|
||||
#include <drivers/io/io_storage.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <drivers/partition/partition.h>
|
||||
#include <lib/semihosting.h>
|
||||
#include <string.h>
|
||||
#include <lib/utils.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include "platform_def.h"
|
||||
|
||||
#define STRATIX10_FIP_BASE (0)
|
||||
#define STRATIX10_FIP_MAX_SIZE (0x1000000)
|
||||
#define STRATIX10_MMC_DATA_BASE (0xffe3c000)
|
||||
#define STRATIX10_MMC_DATA_SIZE (0x2000)
|
||||
|
||||
static const io_dev_connector_t *mmc_dev_con;
|
||||
static const io_dev_connector_t *fip_dev_con;
|
||||
|
||||
static uintptr_t fip_dev_handle;
|
||||
static uintptr_t mmc_dev_handle;
|
||||
|
||||
static const io_uuid_spec_t bl2_uuid_spec = {
|
||||
.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl31_uuid_spec = {
|
||||
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl33_uuid_spec = {
|
||||
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
|
||||
};
|
||||
|
||||
uintptr_t a2_lba_offset;
|
||||
|
||||
static const io_block_spec_t gpt_block_spec = {
|
||||
.offset = 0,
|
||||
.length = MMC_BLOCK_SIZE
|
||||
};
|
||||
|
||||
static int check_mmc(const uintptr_t spec);
|
||||
static int check_fip(const uintptr_t spec);
|
||||
|
||||
static io_block_spec_t mmc_fip_spec = {
|
||||
.offset = STRATIX10_FIP_BASE,
|
||||
.length = STRATIX10_FIP_MAX_SIZE,
|
||||
};
|
||||
|
||||
const char a2[] = {0xa2, 0x0};
|
||||
|
||||
static const io_block_dev_spec_t mmc_dev_spec = {
|
||||
.buffer = {
|
||||
.offset = STRATIX10_MMC_DATA_BASE,
|
||||
.length = MMC_BLOCK_SIZE,
|
||||
},
|
||||
|
||||
.ops = {
|
||||
.read = mmc_read_blocks,
|
||||
.write = mmc_write_blocks,
|
||||
},
|
||||
|
||||
.block_size = MMC_BLOCK_SIZE,
|
||||
};
|
||||
|
||||
struct plat_io_policy {
|
||||
uintptr_t *dev_handle;
|
||||
uintptr_t image_spec;
|
||||
int (*check)(const uintptr_t spec);
|
||||
};
|
||||
|
||||
static const struct plat_io_policy policies[] = {
|
||||
[FIP_IMAGE_ID] = {
|
||||
&mmc_dev_handle,
|
||||
(uintptr_t)&mmc_fip_spec,
|
||||
check_mmc
|
||||
},
|
||||
[BL2_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl2_uuid_spec,
|
||||
check_fip
|
||||
},
|
||||
[BL31_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl31_uuid_spec,
|
||||
check_fip
|
||||
},
|
||||
[BL33_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t) &bl33_uuid_spec,
|
||||
check_fip
|
||||
},
|
||||
[GPT_IMAGE_ID] = {
|
||||
&mmc_dev_handle,
|
||||
(uintptr_t) &gpt_block_spec,
|
||||
check_mmc
|
||||
},
|
||||
};
|
||||
|
||||
static int check_mmc(const uintptr_t spec)
|
||||
{
|
||||
int result;
|
||||
uintptr_t local_handle;
|
||||
|
||||
result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
|
||||
if (result == 0) {
|
||||
result = io_open(mmc_dev_handle, spec, &local_handle);
|
||||
if (result == 0)
|
||||
io_close(local_handle);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static int check_fip(const uintptr_t spec)
|
||||
{
|
||||
int result;
|
||||
uintptr_t local_image_handle;
|
||||
|
||||
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
|
||||
if (result == 0) {
|
||||
result = io_open(fip_dev_handle, spec, &local_image_handle);
|
||||
if (result == 0)
|
||||
io_close(local_image_handle);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
void stratix10_io_setup(void)
|
||||
{
|
||||
int result;
|
||||
|
||||
result = register_io_dev_block(&mmc_dev_con);
|
||||
assert(result == 0);
|
||||
|
||||
result = register_io_dev_fip(&fip_dev_con);
|
||||
assert(result == 0);
|
||||
|
||||
result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
|
||||
&mmc_dev_handle);
|
||||
assert(result == 0);
|
||||
|
||||
result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
|
||||
assert(result == 0);
|
||||
|
||||
partition_init(GPT_IMAGE_ID);
|
||||
|
||||
mmc_fip_spec.offset = get_partition_entry(a2)->start;
|
||||
|
||||
(void)result;
|
||||
}
|
||||
|
||||
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
|
||||
uintptr_t *image_spec)
|
||||
{
|
||||
int result;
|
||||
const struct plat_io_policy *policy;
|
||||
|
||||
assert(image_id < ARRAY_SIZE(policies));
|
||||
|
||||
policy = &policies[image_id];
|
||||
result = policy->check(policy->image_spec);
|
||||
assert(result == 0);
|
||||
|
||||
*image_spec = policy->image_spec;
|
||||
*dev_handle = *(policy->dev_handle);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#
|
||||
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
PLAT_INCLUDES := \
|
||||
-Iplat/intel/soc/stratix10/ \
|
||||
-Iplat/intel/soc/stratix10/include/ \
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := \
|
||||
lib/xlat_tables/xlat_tables_common.c \
|
||||
lib/xlat_tables/aarch64/xlat_tables.c \
|
||||
drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
plat/common/plat_gicv2.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
plat/intel/soc/stratix10/aarch64/platform_common.c \
|
||||
plat/intel/soc/stratix10/aarch64/plat_helpers.S \
|
||||
|
||||
BL2_SOURCES += \
|
||||
drivers/partition/partition.c \
|
||||
drivers/partition/gpt.c \
|
||||
drivers/arm/pl061/pl061_gpio.c \
|
||||
drivers/mmc/mmc.c \
|
||||
drivers/synopsys/emmc/dw_mmc.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/io/io_block.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/gpio/gpio.c \
|
||||
drivers/io/io_memmap.c \
|
||||
plat/intel/soc/stratix10/bl2_plat_setup.c \
|
||||
plat/intel/soc/stratix10/plat_storage.c \
|
||||
plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \
|
||||
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
|
||||
plat/intel/soc/stratix10/soc/s10_handoff.c \
|
||||
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
|
||||
plat/intel/soc/stratix10/soc/s10_pinmux.c \
|
||||
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
|
||||
plat/intel/soc/stratix10/plat_delay_timer.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
plat/intel/soc/stratix10/stratix10_image_load.c \
|
||||
plat/intel/soc/stratix10/soc/s10_system_manager.c \
|
||||
common/desc_image_load.c
|
||||
|
||||
# plat/intel/soc/stratix10/plat_topology.c \
|
||||
|
||||
PROGRAMMABLE_RESET_ADDRESS := 0
|
||||
BL2_AT_EL3 := 1
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_DEF_H__
|
||||
#define __PLATFORM_DEF_H__
|
||||
|
||||
#include <arch.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/interrupt_props.h>
|
||||
#include <common/tbbr/tbbr_img_def.h>
|
||||
#include <drivers/arm/gic_common.h>
|
||||
#include <plat/common/common_def.h>
|
||||
|
||||
|
||||
/* Define next boot image name and offset */
|
||||
#define PLAT_NS_IMAGE_OFFSET 0x50000
|
||||
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform binary types for linking
|
||||
******************************************************************************/
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
/* Stratix 10 supports up to 124GB RAM */
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PRIMARY_CPU 0
|
||||
#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#define PLATFORM_STACK_SIZE 0x2000
|
||||
|
||||
/* PSCI related constant */
|
||||
#define PLAT_NUM_POWER_DOMAINS 5
|
||||
#define PLAT_MAX_PWR_LVL 1
|
||||
#define PLAT_MAX_RET_STATE 1
|
||||
#define PLAT_MAX_OFF_STATE 2
|
||||
#define PLATFORM_SYSTEM_COUNT 1
|
||||
#define PLATFORM_CLUSTER_COUNT 1
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT 4
|
||||
#define PLATFORM_CLUSTER1_CORE_COUNT 0
|
||||
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
|
||||
PLATFORM_CLUSTER0_CORE_COUNT)
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
|
||||
|
||||
/* Interrupt related constant */
|
||||
|
||||
#define INTEL_S10_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define INTEL_S10_IRQ_SEC_SGI_0 8
|
||||
#define INTEL_S10_IRQ_SEC_SGI_1 9
|
||||
#define INTEL_S10_IRQ_SEC_SGI_2 10
|
||||
#define INTEL_S10_IRQ_SEC_SGI_3 11
|
||||
#define INTEL_S10_IRQ_SEC_SGI_4 12
|
||||
#define INTEL_S10_IRQ_SEC_SGI_5 13
|
||||
#define INTEL_S10_IRQ_SEC_SGI_6 14
|
||||
#define INTEL_S10_IRQ_SEC_SGI_7 15
|
||||
|
||||
#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER
|
||||
#define TSP_SEC_MEM_BASE BL32_BASE
|
||||
#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
|
||||
/*******************************************************************************
|
||||
* Platform memory map related constants
|
||||
******************************************************************************/
|
||||
#define DRAM_BASE (0x0)
|
||||
#define DRAM_SIZE (0x80000000)
|
||||
|
||||
#define OCRAM_BASE (0xFFE00000)
|
||||
#define OCRAM_SIZE (0x00100000)
|
||||
|
||||
#define MEM64_BASE (0x0100000000)
|
||||
#define MEM64_SIZE (0x1F00000000)
|
||||
|
||||
#define DEVICE1_BASE (0x80000000)
|
||||
#define DEVICE1_SIZE (0x60000000)
|
||||
|
||||
#define DEVICE2_BASE (0xF7000000)
|
||||
#define DEVICE2_SIZE (0x08E00000)
|
||||
|
||||
#define DEVICE3_BASE (0xFFFC0000)
|
||||
#define DEVICE3_SIZE (0x00008000)
|
||||
|
||||
#define DEVICE4_BASE (0x2000000000)
|
||||
#define DEVICE4_SIZE (0x0100000000)
|
||||
|
||||
/*******************************************************************************
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
|
||||
* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
|
||||
|
||||
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
|
||||
|
||||
#define BL1_RO_BASE (0xffe00000)
|
||||
#define BL1_RO_LIMIT (0xffe0f000)
|
||||
#define BL1_RW_BASE (0xffe10000)
|
||||
#define BL1_RW_LIMIT (0xffe1ffff)
|
||||
#define BL1_RW_SIZE (0x14000)
|
||||
|
||||
#define BL2_BASE (0xffe00000)
|
||||
#define BL2_LIMIT (0xffe1c000)
|
||||
|
||||
#define BL31_BASE (0xffe1c000)
|
||||
#define BL31_LIMIT (0xffe3ffff)
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define MAX_XLAT_TABLES 8
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
||||
/*******************************************************************************
|
||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||
* aligned on the biggest cache line size in the platform. This is known only
|
||||
* to the platform as it might have a combination of integrated and external
|
||||
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
|
||||
* line at any cache level. They could belong to different cpus/clusters &
|
||||
* get written while being protected by different locks causing corruption of
|
||||
* a valid mailbox address.
|
||||
******************************************************************************/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
#define PLAT_GIC_BASE (0xFFFC0000)
|
||||
#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
|
||||
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
|
||||
#define PLAT_GICR_BASE 0
|
||||
|
||||
/*******************************************************************************
|
||||
* UART related constants
|
||||
******************************************************************************/
|
||||
#define PLAT_UART0_BASE (0xFFC02000)
|
||||
#define PLAT_UART1_BASE (0xFFC02100)
|
||||
|
||||
#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
|
||||
|
||||
#define PLAT_BAUDRATE (115200)
|
||||
#define PLAT_UART_CLOCK (100000000)
|
||||
|
||||
/*******************************************************************************
|
||||
* System counter frequency related constants
|
||||
******************************************************************************/
|
||||
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
|
||||
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
|
||||
|
||||
#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE
|
||||
#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE
|
||||
|
||||
/*
|
||||
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
|
||||
grp, GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp)
|
||||
|
||||
#define MAX_IO_HANDLES 4
|
||||
#define MAX_IO_DEVICES 4
|
||||
#define MAX_IO_BLOCK_DEVICES 2
|
||||
|
||||
|
||||
#endif /* __PLATFORM_DEF_H__ */
|
||||
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
|
||||
#include "s10_clock_manager.h"
|
||||
#include "s10_handoff.h"
|
||||
|
||||
|
||||
void wait_pll_lock(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
do {
|
||||
data = mmio_read_32(ALT_CLKMGR + ALT_CLKMGR_STAT);
|
||||
} while ((ALT_CLKMGR_STAT_MAINPLLLOCKED(data) == 0) ||
|
||||
(ALT_CLKMGR_STAT_PERPLLLOCKED(data) == 0));
|
||||
}
|
||||
|
||||
void wait_fsm(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
do {
|
||||
data = mmio_read_32(ALT_CLKMGR + ALT_CLKMGR_STAT);
|
||||
} while (ALT_CLKMGR_STAT_BUSY(data) == ALT_CLKMGR_STAT_BUSY_E_BUSY);
|
||||
}
|
||||
|
||||
void config_clkmgr_handoff(handoff *hoff_ptr)
|
||||
{
|
||||
uint32_t m_div, refclk_div, mscnt, hscnt;
|
||||
|
||||
/* Bypass all mainpllgrp's clocks */
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL +
|
||||
ALT_CLKMGR_MAINPLL_BYPASS,
|
||||
0x7);
|
||||
wait_fsm();
|
||||
/* Bypass all perpllgrp's clocks */
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL +
|
||||
ALT_CLKMGR_PERPLL_BYPASS,
|
||||
0x7f);
|
||||
wait_fsm();
|
||||
|
||||
/* Setup main PLL dividers */
|
||||
m_div = ALT_CLKMGR_MAINPLL_FDBCK_MDIV(hoff_ptr->main_pll_fdbck);
|
||||
refclk_div = ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(
|
||||
hoff_ptr->main_pll_pllglob);
|
||||
mscnt = 200 / ((6 + m_div) / refclk_div);
|
||||
hscnt = (m_div + 6) * mscnt / refclk_div - 9;
|
||||
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB,
|
||||
hoff_ptr->main_pll_pllglob);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_FDBCK,
|
||||
hoff_ptr->main_pll_fdbck);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_VCOCALIB,
|
||||
ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
|
||||
ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC0,
|
||||
hoff_ptr->main_pll_pllc0);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLC1,
|
||||
hoff_ptr->main_pll_pllc1);
|
||||
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCDIV,
|
||||
hoff_ptr->main_pll_nocdiv);
|
||||
|
||||
/* Setup peripheral PLL dividers */
|
||||
m_div = ALT_CLKMGR_PERPLL_FDBCK_MDIV(hoff_ptr->per_pll_fdbck);
|
||||
refclk_div = ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(
|
||||
hoff_ptr->per_pll_pllglob);
|
||||
mscnt = 200 / ((6 + m_div) / refclk_div);
|
||||
hscnt = (m_div + 6) * mscnt / refclk_div - 9;
|
||||
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB,
|
||||
hoff_ptr->per_pll_pllglob);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_FDBCK,
|
||||
hoff_ptr->per_pll_fdbck);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_VCOCALIB,
|
||||
ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
|
||||
ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC0,
|
||||
hoff_ptr->per_pll_pllc0);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLC1,
|
||||
hoff_ptr->per_pll_pllc1);
|
||||
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_GPIODIV,
|
||||
ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(
|
||||
hoff_ptr->per_pll_gpiodiv));
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EMACCTL,
|
||||
hoff_ptr->per_pll_emacctl);
|
||||
|
||||
|
||||
/* Take both PLL out of reset and power up */
|
||||
mmio_setbits_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB,
|
||||
ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
|
||||
ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
|
||||
mmio_setbits_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_PLLGLOB,
|
||||
ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
|
||||
ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
|
||||
|
||||
wait_pll_lock();
|
||||
|
||||
/* Dividers for C2 to C9 only init after PLLs are lock. */
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_MPUCLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR2CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR3CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR4CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR5CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR7CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR8CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR9CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR2CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR3CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR4CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR5CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR6CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR7CLK, 0xff);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR8CLK, 0xff);
|
||||
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_MPUCLK,
|
||||
hoff_ptr->main_pll_mpuclk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_NOCCLK,
|
||||
hoff_ptr->main_pll_nocclk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR2CLK,
|
||||
hoff_ptr->main_pll_cntr2clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR3CLK,
|
||||
hoff_ptr->main_pll_cntr3clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR4CLK,
|
||||
hoff_ptr->main_pll_cntr4clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR5CLK,
|
||||
hoff_ptr->main_pll_cntr5clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR6CLK,
|
||||
hoff_ptr->main_pll_cntr6clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR7CLK,
|
||||
hoff_ptr->main_pll_cntr7clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR8CLK,
|
||||
hoff_ptr->main_pll_cntr8clk);
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_CNTR9CLK,
|
||||
hoff_ptr->main_pll_cntr9clk);
|
||||
|
||||
/* Peripheral PLL Clock Source and Counters/Divider */
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR2CLK,
|
||||
hoff_ptr->per_pll_cntr2clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR3CLK,
|
||||
hoff_ptr->per_pll_cntr3clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR4CLK,
|
||||
hoff_ptr->per_pll_cntr4clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR5CLK,
|
||||
hoff_ptr->per_pll_cntr5clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR6CLK,
|
||||
hoff_ptr->per_pll_cntr6clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR7CLK,
|
||||
hoff_ptr->per_pll_cntr7clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR8CLK,
|
||||
hoff_ptr->per_pll_cntr8clk);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_CNTR9CLK,
|
||||
hoff_ptr->per_pll_cntr9clk);
|
||||
|
||||
/* Take all PLLs out of bypass */
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_BYPASS, 0);
|
||||
wait_fsm();
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_BYPASS, 0);
|
||||
wait_fsm();
|
||||
|
||||
/* Set safe mode/ out of boot mode */
|
||||
mmio_clrbits_32(ALT_CLKMGR + ALT_CLKMGR_CTRL,
|
||||
ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK);
|
||||
wait_fsm();
|
||||
|
||||
/* 10 Enable mainpllgrp's software-managed clock */
|
||||
mmio_write_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_EN,
|
||||
ALT_CLKMGR_MAINPLL_EN_RESET);
|
||||
mmio_write_32(ALT_CLKMGR_PERPLL + ALT_CLKMGR_PERPLL_EN,
|
||||
ALT_CLKMGR_PERPLL_EN_RESET);
|
||||
|
||||
/* Clear loss lock interrupt status register that */
|
||||
/* might be set during configuration */
|
||||
mmio_write_32(ALT_CLKMGR + ALT_CLKMGR_INTRCLR,
|
||||
ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK |
|
||||
ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <assert.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <string.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
|
||||
#include "s10_handoff.h"
|
||||
|
||||
#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \
|
||||
(((x) & 0x0000FF00) << 8) | ((x) << 24))
|
||||
|
||||
int s10_get_handoff(handoff *reverse_hoff_ptr)
|
||||
{
|
||||
int i;
|
||||
uint32_t *buffer;
|
||||
handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET;
|
||||
|
||||
memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff));
|
||||
buffer = (uint32_t *)reverse_hoff_ptr;
|
||||
|
||||
/* convert big indian to little indian */
|
||||
for (i = 0; i < sizeof(handoff) / 4; i++)
|
||||
buffer[i] = SWAP_UINT32(buffer[i]);
|
||||
|
||||
if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER)
|
||||
return -1;
|
||||
if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL)
|
||||
return -1;
|
||||
if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR)
|
||||
return -1;
|
||||
if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA)
|
||||
return -1;
|
||||
if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,401 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <errno.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/delay_timer.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "s10_memory_controller.h"
|
||||
|
||||
#define ALT_CCU_NOC_DI_SET_MSK 0x10
|
||||
|
||||
#define DDR_READ_LATENCY_DELAY 40
|
||||
#define MAX_MEM_CAL_RETRY 3
|
||||
#define PRE_CALIBRATION_DELAY 1
|
||||
#define POST_CALIBRATION_DELAY 1
|
||||
#define TIMEOUT_EMIF_CALIBRATION 100
|
||||
#define CLEAR_EMIF_DELAY 50000
|
||||
#define CLEAR_EMIF_TIMEOUT 0x100000
|
||||
#define TIMEOUT_INT_RESP 10000
|
||||
|
||||
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
|
||||
#define DDR_CONFIG_ELEMENTS (sizeof(ddr_config)/sizeof(uint32_t))
|
||||
|
||||
/* tWR = Min. 15ns constant, see JEDEC standard eg. DDR4 is JESD79-4.pdf */
|
||||
#define tWR_IN_NS 15
|
||||
|
||||
void configure_hmc_adaptor_regs(void);
|
||||
void configure_ddr_sched_ctrl_regs(void);
|
||||
|
||||
/* The followring are the supported configurations */
|
||||
uint32_t ddr_config[] = {
|
||||
/* DDR_CONFIG(Address order,Bank,Column,Row) */
|
||||
/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
|
||||
DDR_CONFIG(0, 3, 10, 12),
|
||||
DDR_CONFIG(0, 3, 9, 13),
|
||||
DDR_CONFIG(0, 3, 10, 13),
|
||||
DDR_CONFIG(0, 3, 9, 14),
|
||||
DDR_CONFIG(0, 3, 10, 14),
|
||||
DDR_CONFIG(0, 3, 10, 15),
|
||||
DDR_CONFIG(0, 3, 11, 14),
|
||||
DDR_CONFIG(0, 3, 11, 15),
|
||||
DDR_CONFIG(0, 3, 10, 16),
|
||||
DDR_CONFIG(0, 3, 11, 16),
|
||||
DDR_CONFIG(0, 3, 12, 15), /* 0xa */
|
||||
/* List for DDR4 only (pinout order > chip, bank, row, column) */
|
||||
DDR_CONFIG(1, 3, 10, 14),
|
||||
DDR_CONFIG(1, 4, 10, 14),
|
||||
DDR_CONFIG(1, 3, 10, 15),
|
||||
DDR_CONFIG(1, 4, 10, 15),
|
||||
DDR_CONFIG(1, 3, 10, 16),
|
||||
DDR_CONFIG(1, 4, 10, 16),
|
||||
DDR_CONFIG(1, 3, 10, 17),
|
||||
DDR_CONFIG(1, 4, 10, 17),
|
||||
};
|
||||
|
||||
static int match_ddr_conf(uint32_t ddr_conf)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
|
||||
if (ddr_conf == ddr_config[i])
|
||||
return i;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int check_hmc_clk(void)
|
||||
{
|
||||
unsigned long timeout = 0;
|
||||
uint32_t hmc_clk;
|
||||
|
||||
do {
|
||||
hmc_clk = mmio_read_32(S10_SYSMGR_CORE_HMC_CLK);
|
||||
if (hmc_clk & S10_SYSMGR_CORE_HMC_CLK_STATUS)
|
||||
break;
|
||||
udelay(1);
|
||||
} while (++timeout < 1000);
|
||||
if (timeout >= 1000)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clear_emif(void)
|
||||
{
|
||||
uint32_t data;
|
||||
unsigned long timeout;
|
||||
|
||||
mmio_write_32(S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL, 0);
|
||||
|
||||
timeout = 0;
|
||||
do {
|
||||
data = mmio_read_32(S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT);
|
||||
if ((data & S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0)
|
||||
break;
|
||||
udelay(CLEAR_EMIF_DELAY);
|
||||
} while (++timeout < CLEAR_EMIF_TIMEOUT);
|
||||
if (timeout >= CLEAR_EMIF_TIMEOUT)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mem_calibration(void)
|
||||
{
|
||||
int status = 0;
|
||||
uint32_t data;
|
||||
unsigned long timeout;
|
||||
unsigned long retry = 0;
|
||||
|
||||
udelay(PRE_CALIBRATION_DELAY);
|
||||
|
||||
do {
|
||||
if (retry != 0)
|
||||
INFO("DDR: Retrying DRAM calibration\n");
|
||||
|
||||
timeout = 0;
|
||||
do {
|
||||
data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT);
|
||||
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
|
||||
break;
|
||||
udelay(1);
|
||||
} while (++timeout < TIMEOUT_EMIF_CALIBRATION);
|
||||
|
||||
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
|
||||
status = clear_emif();
|
||||
if (status)
|
||||
ERROR("Failed to clear Emif\n");
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
} while (++retry < MAX_MEM_CAL_RETRY);
|
||||
|
||||
if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
|
||||
ERROR("DDR: DRAM calibration failed.\n");
|
||||
status = -EIO;
|
||||
} else {
|
||||
INFO("DDR: DRAM calibration success.\n");
|
||||
status = 0;
|
||||
}
|
||||
|
||||
udelay(POST_CALIBRATION_DELAY);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int init_hard_memory_controller(void)
|
||||
{
|
||||
int status;
|
||||
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_DDR, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_CPU0_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK);
|
||||
|
||||
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM0, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1A, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1B, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1C, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1D, S10_CCU_NOC_DI_SET_MSK);
|
||||
mmio_clrbits_32(S10_CCU_IOM_MPRT_MEM1E, S10_CCU_NOC_DI_SET_MSK);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, 0xFFFF0000);
|
||||
mmio_write_32(S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1F);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, 0xFFFF0000);
|
||||
mmio_write_32(S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT, 0x1F);
|
||||
mmio_write_32(S10_SOC_NOC_FW_DDR_SCR_ENABLE, BIT(0) | BIT(8));
|
||||
|
||||
status = check_hmc_clk();
|
||||
if (status) {
|
||||
ERROR("DDR: Error, HMC clock not running\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
mmio_clrbits_32(S10_RSTMGR_BRGMODRST, S10_RSTMGR_BRGMODRST_DDRSCH);
|
||||
|
||||
status = mem_calibration();
|
||||
if (status) {
|
||||
ERROR("DDR: Memory Calibration Failed\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
configure_hmc_adaptor_regs();
|
||||
configure_ddr_sched_ctrl_regs();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void configure_ddr_sched_ctrl_regs(void)
|
||||
{
|
||||
uint32_t data, dram_addr_order, ddr_conf, bank, row, col,
|
||||
rd_to_miss, wr_to_miss, burst_len, burst_len_ddr_clk,
|
||||
burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio,
|
||||
t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles,
|
||||
bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw,
|
||||
faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd;
|
||||
|
||||
INFO("Init HPS NOC's DDR Scheduler.\n");
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG1);
|
||||
dram_addr_order = S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_DRAMADDRW);
|
||||
|
||||
col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data);
|
||||
row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data);
|
||||
bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) +
|
||||
IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(data);
|
||||
|
||||
ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row));
|
||||
|
||||
if (ddr_conf) {
|
||||
mmio_clrsetbits_32(
|
||||
S10_MPFE_DDR_MAIN_SCHED_DDRCONF,
|
||||
S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK,
|
||||
S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(ddr_conf));
|
||||
} else {
|
||||
ERROR("DDR: Cannot find predefined ddrConf configuration.\n");
|
||||
}
|
||||
|
||||
mmio_write_32(S10_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_DRAMTIMING0);
|
||||
rd_latency = S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING0);
|
||||
act_to_act = ACT_TO_ACT(data);
|
||||
t_rcd = ACT_TO_RDWR(data);
|
||||
act_to_act_bank = ACT_TO_ACT_DIFF_BANK(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING1);
|
||||
rd_to_wr = RD_TO_WR(data);
|
||||
bus_rd_to_rd = RD_TO_RD_DIFF_CHIP(data);
|
||||
bus_rd_to_wr = RD_TO_WR_DIFF_CHIP(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING2);
|
||||
t_rtp = RD_TO_PCH(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING3);
|
||||
wr_to_rd = CALTIMING3_WR_TO_RD(data);
|
||||
bus_wr_to_rd = CALTIMING3_WR_TO_RD_DIFF_CHIP(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING4);
|
||||
t_rp = PCH_TO_VALID(data);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
|
||||
bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
|
||||
burst_len = HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(data);
|
||||
burst_len_ddr_clk = burst_len / 2;
|
||||
burst_len_sched_clk = ((burst_len/2) / 2);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG0);
|
||||
switch (S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(data)) {
|
||||
case 1:
|
||||
/* DDR4 - 1333MHz */
|
||||
/* 20 (19.995) clock cycles = 15ns */
|
||||
/* Calculate with rounding */
|
||||
tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ?
|
||||
((tWR_IN_NS * 1333) / 1000) + 1 :
|
||||
((tWR_IN_NS * 1333) / 1000);
|
||||
break;
|
||||
default:
|
||||
/* Others - 1066MHz or slower */
|
||||
/* 16 (15.990) clock cycles = 15ns */
|
||||
/* Calculate with rounding */
|
||||
tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ?
|
||||
((tWR_IN_NS * 1066) / 1000) + 1 :
|
||||
((tWR_IN_NS * 1066) / 1000);
|
||||
break;
|
||||
}
|
||||
|
||||
rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk;
|
||||
wr_to_miss = ((rd_latency + burst_len_ddr_clk + 2 + tw_rin_clk_cycles)
|
||||
/ 2) - rd_to_wr + t_rp + t_rcd;
|
||||
|
||||
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DDRTIMING,
|
||||
bw_ratio << DDRTIMING_BWRATIO_OFST |
|
||||
wr_to_rd << DDRTIMING_WRTORD_OFST|
|
||||
rd_to_wr << DDRTIMING_RDTOWR_OFST |
|
||||
burst_len_sched_clk << DDRTIMING_BURSTLEN_OFST |
|
||||
wr_to_miss << DDRTIMING_WRTOMISS_OFST |
|
||||
rd_to_miss << DDRTIMING_RDTOMISS_OFST |
|
||||
act_to_act << DDRTIMING_ACTTOACT_OFST);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL));
|
||||
bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0);
|
||||
|
||||
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DDRMODE,
|
||||
bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST |
|
||||
auto_precharge << DDRMODE_AUTOPRECHARGE_OFST);
|
||||
|
||||
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_READLATENCY,
|
||||
(rd_latency / 2) + DDR_READ_LATENCY_DELAY);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING9);
|
||||
faw = S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(data);
|
||||
|
||||
faw_bank = 1; // always 1 because we always have 4 bank DDR.
|
||||
|
||||
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_ACTIVATE,
|
||||
faw_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST |
|
||||
faw << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST |
|
||||
act_to_act_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST);
|
||||
|
||||
mmio_write_32(S10_MPFE_DDR_MAIN_SCHED_DEVTODEV,
|
||||
bus_rd_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST |
|
||||
bus_rd_to_wr << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST |
|
||||
bus_wr_to_rd << S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST);
|
||||
|
||||
}
|
||||
|
||||
unsigned long get_physical_dram_size(void)
|
||||
{
|
||||
uint32_t data;
|
||||
unsigned long ram_addr_width, ram_ext_if_io_width;
|
||||
|
||||
data = mmio_read_32(S10_MPFE_HMC_ADP_DDRIOCTRL);
|
||||
switch (S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(data)) {
|
||||
case 0:
|
||||
ram_ext_if_io_width = 16;
|
||||
break;
|
||||
case 1:
|
||||
ram_ext_if_io_width = 32;
|
||||
break;
|
||||
case 2:
|
||||
ram_ext_if_io_width = 64;
|
||||
break;
|
||||
default:
|
||||
ram_ext_if_io_width = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_REG_DRAMADDRW);
|
||||
ram_addr_width = IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(data) +
|
||||
IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(data) +
|
||||
IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(data) +
|
||||
IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(data) +
|
||||
IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(data);
|
||||
|
||||
return (1 << ram_addr_width) * (ram_ext_if_io_width / 8);
|
||||
}
|
||||
|
||||
|
||||
|
||||
void configure_hmc_adaptor_regs(void)
|
||||
{
|
||||
uint32_t data;
|
||||
uint32_t dram_io_width;
|
||||
|
||||
dram_io_width = S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(
|
||||
mmio_read_32(S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST));
|
||||
|
||||
dram_io_width = (dram_io_width & 0xFF) >> 5;
|
||||
|
||||
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL,
|
||||
S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK,
|
||||
dram_io_width << S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST);
|
||||
|
||||
mmio_write_32(S10_MPFE_HMC_ADP_HPSINTFCSEL,
|
||||
S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE);
|
||||
|
||||
data = mmio_read_32(S10_MPFE_IOHMC_REG_CTRLCFG1);
|
||||
if (data & (1 << S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) {
|
||||
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1,
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK);
|
||||
|
||||
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2,
|
||||
S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK,
|
||||
S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK);
|
||||
|
||||
mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1,
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK |
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK,
|
||||
S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK);
|
||||
|
||||
} else {
|
||||
INFO("ECC is disabled.\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#include "s10_pinmux.h"
|
||||
|
||||
const uint32_t sysmgr_pinmux_array_sel[] = {
|
||||
0x00000000, 0x00000001, /* usb */
|
||||
0x00000004, 0x00000001,
|
||||
0x00000008, 0x00000001,
|
||||
0x0000000c, 0x00000001,
|
||||
0x00000010, 0x00000001,
|
||||
0x00000014, 0x00000001,
|
||||
0x00000018, 0x00000001,
|
||||
0x0000001c, 0x00000001,
|
||||
0x00000020, 0x00000001,
|
||||
0x00000024, 0x00000001,
|
||||
0x00000028, 0x00000001,
|
||||
0x0000002c, 0x00000001,
|
||||
0x00000030, 0x00000000, /* emac0 */
|
||||
0x00000034, 0x00000000,
|
||||
0x00000038, 0x00000000,
|
||||
0x0000003c, 0x00000000,
|
||||
0x00000040, 0x00000000,
|
||||
0x00000044, 0x00000000,
|
||||
0x00000048, 0x00000000,
|
||||
0x0000004c, 0x00000000,
|
||||
0x00000050, 0x00000000,
|
||||
0x00000054, 0x00000000,
|
||||
0x00000058, 0x00000000,
|
||||
0x0000005c, 0x00000000,
|
||||
0x00000060, 0x00000008, /* gpio1 */
|
||||
0x00000064, 0x00000008,
|
||||
0x00000068, 0x00000005, /* uart0 tx */
|
||||
0x0000006c, 0x00000005, /* uart 0 rx */
|
||||
0x00000070, 0x00000008, /* gpio */
|
||||
0x00000074, 0x00000008,
|
||||
0x00000078, 0x00000004, /* i2c1 */
|
||||
0x0000007c, 0x00000004,
|
||||
0x00000080, 0x00000007, /* jtag */
|
||||
0x00000084, 0x00000007,
|
||||
0x00000088, 0x00000007,
|
||||
0x0000008c, 0x00000007,
|
||||
0x00000090, 0x00000001, /* sdmmc data0 */
|
||||
0x00000094, 0x00000001,
|
||||
0x00000098, 0x00000001,
|
||||
0x0000009c, 0x00000001,
|
||||
0x00000100, 0x00000001,
|
||||
0x00000104, 0x00000001, /* sdmmc.data3 */
|
||||
0x00000108, 0x00000008, /* loan */
|
||||
0x0000010c, 0x00000008, /* gpio */
|
||||
0x00000110, 0x00000008,
|
||||
0x00000114, 0x00000008, /* gpio1.io21 */
|
||||
0x00000118, 0x00000005, /* mdio0.mdio */
|
||||
0x0000011c, 0x00000005 /* mdio0.mdc */
|
||||
};
|
||||
|
||||
const uint32_t sysmgr_pinmux_array_ctrl[] = {
|
||||
0x00000000, 0x00502c38, /* Q1_1 */
|
||||
0x00000004, 0x00102c38,
|
||||
0x00000008, 0x00502c38,
|
||||
0x0000000c, 0x00502c38,
|
||||
0x00000010, 0x00502c38,
|
||||
0x00000014, 0x00502c38,
|
||||
0x00000018, 0x00502c38,
|
||||
0x0000001c, 0x00502c38,
|
||||
0x00000020, 0x00502c38,
|
||||
0x00000024, 0x00502c38,
|
||||
0x00000028, 0x00502c38,
|
||||
0x0000002c, 0x00502c38,
|
||||
0x00000030, 0x00102c38, /* Q2_1 */
|
||||
0x00000034, 0x00102c38,
|
||||
0x00000038, 0x00502c38,
|
||||
0x0000003c, 0x00502c38,
|
||||
0x00000040, 0x00102c38,
|
||||
0x00000044, 0x00102c38,
|
||||
0x00000048, 0x00502c38,
|
||||
0x0000004c, 0x00502c38,
|
||||
0x00000050, 0x00102c38,
|
||||
0x00000054, 0x00102c38,
|
||||
0x00000058, 0x00502c38,
|
||||
0x0000005c, 0x00502c38,
|
||||
0x00000060, 0x00502c38, /* Q3_1 */
|
||||
0x00000064, 0x00502c38,
|
||||
0x00000068, 0x00102c38,
|
||||
0x0000006c, 0x00502c38,
|
||||
0x000000d0, 0x00502c38,
|
||||
0x000000d4, 0x00502c38,
|
||||
0x000000d8, 0x00542c38,
|
||||
0x000000dc, 0x00542c38,
|
||||
0x000000e0, 0x00502c38,
|
||||
0x000000e4, 0x00502c38,
|
||||
0x000000e8, 0x00102c38,
|
||||
0x000000ec, 0x00502c38,
|
||||
0x000000f0, 0x00502c38, /* Q4_1 */
|
||||
0x000000f4, 0x00502c38,
|
||||
0x000000f8, 0x00102c38,
|
||||
0x000000fc, 0x00502c38,
|
||||
0x00000100, 0x00502c38,
|
||||
0x00000104, 0x00502c38,
|
||||
0x00000108, 0x00102c38,
|
||||
0x0000010c, 0x00502c38,
|
||||
0x00000110, 0x00502c38,
|
||||
0x00000114, 0x00502c38,
|
||||
0x00000118, 0x00542c38,
|
||||
0x0000011c, 0x00102c38
|
||||
};
|
||||
|
||||
const uint32_t sysmgr_pinmux_array_fpga[] = {
|
||||
0x00000000, 0x00000000,
|
||||
0x00000004, 0x00000000,
|
||||
0x00000008, 0x00000000,
|
||||
0x0000000c, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000014, 0x00000000,
|
||||
0x00000018, 0x00000000,
|
||||
0x0000001c, 0x00000000,
|
||||
0x00000020, 0x00000000,
|
||||
0x00000028, 0x00000000,
|
||||
0x0000002c, 0x00000000,
|
||||
0x00000030, 0x00000000,
|
||||
0x00000034, 0x00000000,
|
||||
0x00000038, 0x00000000,
|
||||
0x0000003c, 0x00000000,
|
||||
0x00000040, 0x00000000,
|
||||
0x00000044, 0x00000000,
|
||||
0x00000048, 0x00000000,
|
||||
0x00000050, 0x00000000,
|
||||
0x00000054, 0x00000000,
|
||||
0x00000058, 0x0000002a
|
||||
};
|
||||
|
||||
const uint32_t sysmgr_pinmux_array_iodelay[] = {
|
||||
0x00000000, 0x00000000,
|
||||
0x00000004, 0x00000000,
|
||||
0x00000008, 0x00000000,
|
||||
0x0000000c, 0x00000000,
|
||||
0x00000010, 0x00000000,
|
||||
0x00000014, 0x00000000,
|
||||
0x00000018, 0x00000000,
|
||||
0x0000001c, 0x00000000,
|
||||
0x00000020, 0x00000000,
|
||||
0x00000024, 0x00000000,
|
||||
0x00000028, 0x00000000,
|
||||
0x0000002c, 0x00000000,
|
||||
0x00000030, 0x00000000,
|
||||
0x00000034, 0x00000000,
|
||||
0x00000038, 0x00000000,
|
||||
0x0000003c, 0x00000000,
|
||||
0x00000040, 0x00000000,
|
||||
0x00000044, 0x00000000,
|
||||
0x00000048, 0x00000000,
|
||||
0x0000004c, 0x00000000,
|
||||
0x00000050, 0x00000000,
|
||||
0x00000054, 0x00000000,
|
||||
0x00000058, 0x00000000,
|
||||
0x0000005c, 0x00000000,
|
||||
0x00000060, 0x00000000,
|
||||
0x00000064, 0x00000000,
|
||||
0x00000068, 0x00000000,
|
||||
0x0000006c, 0x00000000,
|
||||
0x00000070, 0x00000000,
|
||||
0x00000074, 0x00000000,
|
||||
0x00000078, 0x00000000,
|
||||
0x0000007c, 0x00000000,
|
||||
0x00000080, 0x00000000,
|
||||
0x00000084, 0x00000000,
|
||||
0x00000088, 0x00000000,
|
||||
0x0000008c, 0x00000000,
|
||||
0x00000090, 0x00000000,
|
||||
0x00000094, 0x00000000,
|
||||
0x00000098, 0x00000000,
|
||||
0x0000009c, 0x00000000,
|
||||
0x00000100, 0x00000000,
|
||||
0x00000104, 0x00000000,
|
||||
0x00000108, 0x00000000,
|
||||
0x0000010c, 0x00000000,
|
||||
0x00000110, 0x00000000,
|
||||
0x00000114, 0x00000000,
|
||||
0x00000118, 0x00000000,
|
||||
0x0000011c, 0x00000000
|
||||
};
|
||||
|
||||
void config_pinmux(handoff *hoff_ptr)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < 96; i += 2) {
|
||||
mmio_write_32(S10_PINMUX_PIN0SEL +
|
||||
hoff_ptr->pinmux_sel_array[i],
|
||||
hoff_ptr->pinmux_sel_array[i+1]);
|
||||
}
|
||||
|
||||
for (i = 0; i < 96; i += 2) {
|
||||
mmio_write_32(S10_PINMUX_IO0CTRL +
|
||||
hoff_ptr->pinmux_io_array[i],
|
||||
hoff_ptr->pinmux_io_array[i+1]);
|
||||
}
|
||||
|
||||
for (i = 0; i < 42; i += 2) {
|
||||
mmio_write_32(S10_PINMUX_PINMUX_EMAC0_USEFPGA +
|
||||
hoff_ptr->pinmux_fpga_array[i],
|
||||
hoff_ptr->pinmux_fpga_array[i+1]);
|
||||
}
|
||||
|
||||
for (i = 0; i < 96; i += 2) {
|
||||
mmio_write_32(S10_PINMUX_IO0_DELAY +
|
||||
hoff_ptr->pinmux_iodelay_array[i],
|
||||
hoff_ptr->pinmux_iodelay_array[i+1]);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <common/bl_common.h>
|
||||
#include <common/debug.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <drivers/console.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <platform_private.h>
|
||||
#include "s10_reset_manager.h"
|
||||
|
||||
void deassert_peripheral_reset(void)
|
||||
{
|
||||
mmio_clrbits_32(S10_RSTMGR_PER1MODRST,
|
||||
S10_RSTMGR_PER1MODRST_WATCHDOG0 |
|
||||
S10_RSTMGR_PER1MODRST_WATCHDOG1 |
|
||||
S10_RSTMGR_PER1MODRST_WATCHDOG2 |
|
||||
S10_RSTMGR_PER1MODRST_WATCHDOG3 |
|
||||
S10_RSTMGR_PER1MODRST_L4SYSTIMER0 |
|
||||
S10_RSTMGR_PER1MODRST_L4SYSTIMER1 |
|
||||
S10_RSTMGR_PER1MODRST_SPTIMER0 |
|
||||
S10_RSTMGR_PER1MODRST_SPTIMER1 |
|
||||
S10_RSTMGR_PER1MODRST_I2C0 |
|
||||
S10_RSTMGR_PER1MODRST_I2C1 |
|
||||
S10_RSTMGR_PER1MODRST_I2C2 |
|
||||
S10_RSTMGR_PER1MODRST_I2C3 |
|
||||
S10_RSTMGR_PER1MODRST_I2C4 |
|
||||
S10_RSTMGR_PER1MODRST_UART0 |
|
||||
S10_RSTMGR_PER1MODRST_UART1 |
|
||||
S10_RSTMGR_PER1MODRST_GPIO0 |
|
||||
S10_RSTMGR_PER1MODRST_GPIO1);
|
||||
|
||||
mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
|
||||
S10_RSTMGR_PER0MODRST_EMAC0OCP |
|
||||
S10_RSTMGR_PER0MODRST_EMAC1OCP |
|
||||
S10_RSTMGR_PER0MODRST_EMAC2OCP |
|
||||
S10_RSTMGR_PER0MODRST_USB0OCP |
|
||||
S10_RSTMGR_PER0MODRST_USB1OCP |
|
||||
S10_RSTMGR_PER0MODRST_NANDOCP |
|
||||
S10_RSTMGR_PER0MODRST_SDMMCOCP |
|
||||
S10_RSTMGR_PER0MODRST_DMAOCP);
|
||||
|
||||
mmio_clrbits_32(S10_RSTMGR_PER0MODRST,
|
||||
S10_RSTMGR_PER0MODRST_EMAC0 |
|
||||
S10_RSTMGR_PER0MODRST_EMAC1 |
|
||||
S10_RSTMGR_PER0MODRST_EMAC2 |
|
||||
S10_RSTMGR_PER0MODRST_USB0 |
|
||||
S10_RSTMGR_PER0MODRST_USB1 |
|
||||
S10_RSTMGR_PER0MODRST_NAND |
|
||||
S10_RSTMGR_PER0MODRST_SDMMC |
|
||||
S10_RSTMGR_PER0MODRST_DMA |
|
||||
S10_RSTMGR_PER0MODRST_SPIM0 |
|
||||
S10_RSTMGR_PER0MODRST_SPIM1 |
|
||||
S10_RSTMGR_PER0MODRST_SPIS0 |
|
||||
S10_RSTMGR_PER0MODRST_SPIS1 |
|
||||
S10_RSTMGR_PER0MODRST_EMACPTP |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF0 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF1 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF2 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF3 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF4 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF5 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF6 |
|
||||
S10_RSTMGR_PER0MODRST_DMAIF7);
|
||||
|
||||
}
|
||||
|
||||
void config_hps_hs_before_warm_reset(void)
|
||||
{
|
||||
uint32_t or_mask = 0;
|
||||
|
||||
or_mask |= S10_RSTMGR_HDSKEN_SDRSELFREFEN;
|
||||
or_mask |= S10_RSTMGR_HDSKEN_FPGAHSEN;
|
||||
or_mask |= S10_RSTMGR_HDSKEN_ETRSTALLEN;
|
||||
or_mask |= S10_RSTMGR_HDSKEN_L2FLUSHEN;
|
||||
or_mask |= S10_RSTMGR_HDSKEN_L3NOC_DBG;
|
||||
or_mask |= S10_RSTMGR_HDSKEN_DEBUG_L3NOC;
|
||||
|
||||
mmio_setbits_32(S10_RSTMGR_HDSKEN, or_mask);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (c) 2019, Intel Corporation. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/utils_def.h>
|
||||
#include "s10_system_manager.h"
|
||||
|
||||
void enable_nonsecure_access(void)
|
||||
{
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
|
||||
DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
|
||||
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
|
||||
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
|
||||
|
||||
mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
|
||||
mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/desc_image_load.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* This function flushes the data structures so that they are visible
|
||||
* in memory for the next BL image.
|
||||
******************************************************************************/
|
||||
void plat_flush_next_bl_params(void)
|
||||
{
|
||||
flush_bl_params_desc();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the list of loadable images.
|
||||
******************************************************************************/
|
||||
bl_load_info_t *plat_get_bl_image_load_info(void)
|
||||
{
|
||||
return get_bl_load_info_from_mem_params_desc();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the list of executable images.
|
||||
******************************************************************************/
|
||||
bl_params_t *plat_get_next_bl_params(void)
|
||||
{
|
||||
return get_next_bl_params_from_mem_params_desc();
|
||||
}
|
||||
Loading…
Reference in New Issue