Tegra186: update t18x_ari.h to v3.1

This patch updates the ARI header file to v3.1.

Change-Id: I3e58cf50d27fb6e72062bb9d9782b75296b32025
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2017-01-04 10:52:54 -08:00
parent 83f3f536e5
commit 6d6bbc88d1
1 changed files with 14 additions and 1 deletions

View File

@ -41,7 +41,7 @@
enum {
TEGRA_ARI_VERSION_MAJOR = 3,
TEGRA_ARI_VERSION_MINOR = 0,
TEGRA_ARI_VERSION_MINOR = 1,
};
typedef enum {
@ -87,6 +87,7 @@ typedef enum {
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0,
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1,
TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2,
TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3,
} tegra_ari_misc_ccplex_index_t;
typedef enum {
@ -226,6 +227,7 @@ typedef enum {
TEGRA_ARI_MCA_RD_WR_CCE = 3,
TEGRA_ARI_MCA_RD_WR_CQX = 4,
TEGRA_ARI_MCA_RD_WR_CTU = 5,
TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7,
TEGRA_ARI_MCA_RD_BANK_INFO = 0x0f,
TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10,
TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11,
@ -393,6 +395,17 @@ typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0, 0),
} tegra_ari_mca_aserr5_bitmasks_t;
typedef enum {
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0, 15),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58, 58),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59, 59),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60, 60),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61, 61),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62, 62),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63, 63),
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0, 63),
} tegra_ari_mca_serr1_bitmasks_t;
#undef TEGRA_ARI_ENUM_MASK_LSB_MSB
typedef enum {