Merge changes I8ea4ea58,I1f0b4aab,I2cccad40 into integration
* changes: marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU marvell: uart: a3720: Fix comments in console_a3700_core_init() function
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commit
6e86102317
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@ -60,10 +60,10 @@ func console_a3700_core_init
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str w3, [x0, #UART_POSSR_REG]
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str w3, [x0, #UART_POSSR_REG]
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/*
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/*
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* Wait for the TX (THR and TSR) to be empty. If wait for 20ms, the TX FIFO is
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* Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is
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* still not empty, TX FIFO will reset by all means.
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* still not empty, TX FIFO will reset by all means.
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*/
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*/
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mov w1, #20 /* max time out 20ms */
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mov w1, #30 /* max time out 30 * 100 us */
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2:
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2:
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/* Check whether TX (THR and TSR) is empty */
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/* Check whether TX (THR and TSR) is empty */
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ldr w3, [x0, #UART_STATUS_REG]
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ldr w3, [x0, #UART_STATUS_REG]
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@ -72,13 +72,13 @@ func console_a3700_core_init
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b.ne 4f
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b.ne 4f
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/* Delay */
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/* Delay */
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mov w2, #30000
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mov w2, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */
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3:
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3:
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sub w2, w2, #1
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sub w2, w2, #1
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cmp w2, #0
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cmp w2, #0
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b.ne 3b
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b.ne 3b
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/* Check whether 10ms is waited */
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/* Check whether wait timeout expired */
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sub w1, w1, #1
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sub w1, w1, #1
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cmp w1, #0
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cmp w1, #0
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b.ne 2b
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b.ne 2b
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