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feat(cpu): add support for Cortex-X1 

This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A.
Follow-up patches will add selected errata workarounds for this CPU.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I4a3d50a98bf55a555bfaefeed5c7b88a35e3bc21
This commit is contained in:
Okash Khawaja 2022-04-21 10:59:34 +01:00 committed by Joanna Farley
parent aeef2c22da
commit 6e8eca78e5
2 changed files with 95 additions and 0 deletions
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24
include/lib/cpus/aarch64/cortex_x1.h Normal file
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/*
* Copyright (c) 2022, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CORTEX_X1_H
#define CORTEX_X1_H
/* Cortex-X1 MIDR for r1p0 */
#define CORTEX_X1_MIDR U(0x411fd440)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_X1_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_X1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_X1_CORE_PWRDN_EN_MASK U(0x1)
#endif /* CORTEX_X1_H */

71
lib/cpus/aarch64/cortex_x1.S Normal file
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/*
* Copyright (c) 2022, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <cortex_x1.h>
#include <cpu_macros.S>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
func cortex_x1_reset_func
ret
endfunc cortex_x1_reset_func
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_x1_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
msr CORTEX_X1_CPUPWRCTLR_EL1, x0
isb
ret
endfunc cortex_x1_core_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex X1. Must follow AAPCS.
*/
func cortex_x1_errata_report
ret
endfunc cortex_x1_errata_report
#endif
/* ---------------------------------------------
* This function provides Cortex X1 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.cortex_x1_regs, "aS"
cortex_x1_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func cortex_x1_cpu_reg_dump
adr x6, cortex_x1_regs
mrs x8, CORTEX_X1_CPUECTLR_EL1
ret
endfunc cortex_x1_cpu_reg_dump
declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \
cortex_x1_reset_func, \
cortex_x1_core_pwr_dwn