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Merge changes from topic "tf-cleanup" into integration 

* changes:
  plat/arm: Move fconf population after the enablement of MMU
  lib/fconf: Update 'set_fw_config_info' function
  lib/fconf: Update data type of config max size
  plat/arm: Check the need for firmware update only once
  plat/arm: sgm: Use consistent name for tb fw config node
This commit is contained in:
Manish Pandey 2020-07-23 13:16:34 +00:00 committed by TrustedFirmware Code Review
parent 3ee148d643 a07c101a4d
commit 710b313cb7
11 changed files with 126 additions and 64 deletions
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7
include/lib/fconf/fconf_dyn_cfg_getter.h
View File

@ -14,14 +14,15 @@
struct dyn_cfg_dtb_info_t {
uintptr_t config_addr;
size_t config_max_size;
uint32_t config_max_size;
unsigned int config_id;
};
struct dyn_cfg_dtb_info_t *dyn_cfg_dtb_info_getter(unsigned int config_id);
int fconf_populate_dtb_registry(uintptr_t config);
/* Set fw_config information in global DTB array */
void set_fw_config_info(uintptr_t config_addr, uint32_t config_max_size);
/* Set config information in global DTB array */
void set_config_info(uintptr_t config_addr, uint32_t config_max_size,
unsigned int config_id);
#endif /* FCONF_DYN_CFG_GETTER_H */

9
include/plat/arm/common/arm_def.h
View File

@ -294,12 +294,19 @@
#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
V2M_FLASH_BLOCK_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define ARM_BL_REGIONS 6
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)

3
lib/fconf/fconf.c
View File

@ -32,8 +32,7 @@ int fconf_load_config(unsigned int image_id)
assert(config_info != NULL);
config_image_info.image_base = config_info->config_addr;
config_image_info.image_max_size =
(uint32_t)config_info->config_max_size;
config_image_info.image_max_size = config_info->config_max_size;
VERBOSE("FCONF: Loading config with image ID: %d\n", image_id);
err = load_auth_image(image_id, &config_image_info);

68
lib/fconf/fconf_dyn_cfg_getter.c
View File

@ -14,63 +14,56 @@
/* We currently use FW, TB_FW, SOC_FW, TOS_FW, NT_FW and HW configs */
#define MAX_DTB_INFO U(6)
/*
* Compile time assert if FW_CONFIG_ID is 0 which is more
* unlikely as 0 is a valid image ID for FIP as per the current
* code but still to avoid code breakage in case of unlikely
* event when image IDs get changed.
*/
CASSERT(FW_CONFIG_ID != U(0), assert_invalid_fw_config_id);
static struct dyn_cfg_dtb_info_t dtb_infos[MAX_DTB_INFO];
static OBJECT_POOL_ARRAY(dtb_info_pool, dtb_infos);
/*
* This function is used to alloc memory for fw config information from
* global pool and set fw configuration information.
* Specifically used by BL1 to set fw_config information in global array
* This function is used to alloc memory for config information from
* global pool and set the configuration information.
*/
void set_fw_config_info(uintptr_t config_addr, uint32_t config_max_size)
void set_config_info(uintptr_t config_addr, uint32_t config_max_size,
unsigned int config_id)
{
struct dyn_cfg_dtb_info_t *dtb_info;
dtb_info = pool_alloc(&dtb_info_pool);
dtb_info->config_addr = config_addr;
dtb_info->config_max_size = config_max_size;
dtb_info->config_id = FW_CONFIG_ID;
dtb_info->config_id = config_id;
}
struct dyn_cfg_dtb_info_t *dyn_cfg_dtb_info_getter(unsigned int config_id)
{
unsigned int index;
struct dyn_cfg_dtb_info_t *info;
/* Positions index to the proper config-id */
for (index = 0; index < MAX_DTB_INFO; index++) {
for (index = 0U; index < MAX_DTB_INFO; index++) {
if (dtb_infos[index].config_id == config_id) {
info = &dtb_infos[index];
break;
return &dtb_infos[index];
}
}
if (index == MAX_DTB_INFO) {
WARN("FCONF: Invalid config id %u\n", config_id);
info = NULL;
}
WARN("FCONF: Invalid config id %u\n", config_id);
return info;
return NULL;
}
int fconf_populate_dtb_registry(uintptr_t config)
{
int rc;
int node, child;
struct dyn_cfg_dtb_info_t *dtb_info;
/* As libfdt use void *, we can't avoid this cast */
const void *dtb = (void *)config;
/*
* Compile time assert if FW_CONFIG_ID is 0 which is more
* unlikely as 0 is a valid image id for FIP as per the current
* code but still to avoid code breakage in case of unlikely
* event when image ids gets changed.
*/
CASSERT(FW_CONFIG_ID != 0, assert_invalid_fw_config_id);
/*
* In case of BL1, fw_config dtb information is already
* populated in global dtb_infos array by 'set_fw_config_info'
@ -80,11 +73,9 @@ int fconf_populate_dtb_registry(uintptr_t config)
* Other BLs, satisfy below check and populate fw_config information
* in global dtb_infos array.
*/
if (dtb_infos[0].config_id == 0) {
dtb_info = pool_alloc(&dtb_info_pool);
dtb_info->config_addr = config;
dtb_info->config_max_size = fdt_totalsize(dtb);
dtb_info->config_id = FW_CONFIG_ID;
if (dtb_infos[0].config_id == 0U) {
uint32_t config_max_size = fdt_totalsize(dtb);
set_config_info(config, config_max_size, FW_CONFIG_ID);
}
/* Find the node offset point to "fconf,dyn_cfg-dtb_registry" compatible property */
@ -96,37 +87,36 @@ int fconf_populate_dtb_registry(uintptr_t config)
}
fdt_for_each_subnode(child, dtb, node) {
uint32_t val32;
uint32_t config_max_size, config_id;
uintptr_t config_addr;
uint64_t val64;
dtb_info = pool_alloc(&dtb_info_pool);
/* Read configuration dtb information */
rc = fdt_read_uint64(dtb, child, "load-address", &val64);
if (rc < 0) {
ERROR("FCONF: Incomplete configuration property in dtb-registry.\n");
return rc;
}
dtb_info->config_addr = (uintptr_t)val64;
config_addr = (uintptr_t)val64;
rc = fdt_read_uint32(dtb, child, "max-size", &val32);
rc = fdt_read_uint32(dtb, child, "max-size", &config_max_size);
if (rc < 0) {
ERROR("FCONF: Incomplete configuration property in dtb-registry.\n");
return rc;
}
dtb_info->config_max_size = val32;
rc = fdt_read_uint32(dtb, child, "id", &val32);
rc = fdt_read_uint32(dtb, child, "id", &config_id);
if (rc < 0) {
ERROR("FCONF: Incomplete configuration property in dtb-registry.\n");
return rc;
}
dtb_info->config_id = val32;
VERBOSE("FCONF: dyn_cfg.dtb_registry cell found with:\n");
VERBOSE("\tload-address = %lx\n", dtb_info->config_addr);
VERBOSE("\tmax-size = 0x%zx\n", dtb_info->config_max_size);
VERBOSE("\tconfig-id = %u\n", dtb_info->config_id);
VERBOSE("\tload-address = %lx\n", config_addr);
VERBOSE("\tmax-size = 0x%x\n", config_max_size);
VERBOSE("\tconfig-id = %u\n", config_id);
set_config_info(config_addr, config_max_size, config_id);
}
if ((child < 0) && (child != -FDT_ERR_NOTFOUND)) {

18
plat/arm/board/a5ds/include/platform_def.h
View File

@ -151,11 +151,19 @@
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define ARM_BL_REGIONS 6
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
@ -194,6 +202,12 @@
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*
* Define limit of firmware configuration memory:
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
@ -221,6 +235,8 @@
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ (PAGE_SIZE / 2U))
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)

23
plat/arm/board/corstone700/common/include/platform_def.h
View File

@ -92,11 +92,24 @@
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
/*
* Boot parameters passed from BL2 to BL31/BL32 are stored here
*/
#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ (PAGE_SIZE / 2U))
/*
* Define limit of firmware configuration memory:
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 2
#define ARM_BL_REGIONS 3
#define PLAT_ARM_MMAP_ENTRIES 8
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
@ -201,6 +214,14 @@
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
#define CORSTONE700_DEVICE_BASE (0x1A000000)
#define CORSTONE700_DEVICE_SIZE (0x26000000)
#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \

22
plat/arm/board/fvp_ve/include/platform_def.h
View File

@ -120,11 +120,20 @@
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define ARM_BL_REGIONS 6
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
@ -173,7 +182,14 @@
* and limit. Leave enough space of BL2 meminfo.
*/
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
+ (PAGE_SIZE / 2U))
/*
* Define limit of firmware configuration memory:
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/*******************************************************************************
* BL1 specific defines.
@ -205,6 +221,8 @@
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ (PAGE_SIZE / 2U))
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)

11
plat/arm/common/arm_bl1_setup.c
View File

@ -54,6 +54,9 @@
/* Data structure which holds the extents of the trusted SRAM for BL1*/
static meminfo_t bl1_tzram_layout;
/* Boolean variable to hold condition whether firmware update needed or not */
static bool is_fwu_needed;
struct meminfo *bl1_plat_sec_mem_layout(void)
{
return &bl1_tzram_layout;
@ -152,15 +155,15 @@ void arm_bl1_platform_setup(void)
plat_arm_io_setup();
/* Check if we need FWU before further processing */
err = plat_arm_bl1_fwu_needed();
if (err) {
is_fwu_needed = plat_arm_bl1_fwu_needed();
if (is_fwu_needed) {
ERROR("Skip platform setup as FWU detected\n");
return;
}
/* Set global DTB info for fixed fw_config information */
fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
set_fw_config_info(ARM_FW_CONFIG_BASE, fw_config_max_size);
set_config_info(ARM_FW_CONFIG_BASE, fw_config_max_size, FW_CONFIG_ID);
/* Fill the device tree information struct with the info from the config dtb */
err = fconf_load_config(FW_CONFIG_ID);
@ -247,5 +250,5 @@ bool plat_arm_bl1_fwu_needed(void)
******************************************************************************/
unsigned int bl1_plat_get_next_image_id(void)
{
return plat_arm_bl1_fwu_needed() ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
}

25
plat/arm/common/arm_bl2_setup.c
View File

@ -26,6 +26,9 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
/* Base address of fw_config received from BL1 */
static uintptr_t fw_config_base;
/*
* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
* for `meminfo_t` data structure and fw_configs passed from BL1.
@ -57,21 +60,13 @@ CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
void arm_bl2_early_platform_setup(uintptr_t fw_config,
struct meminfo *mem_layout)
{
const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
/* Initialize the console to provide early debug support */
arm_console_boot_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", fw_config);
/* TB_FW_CONFIG was also loaded by BL1 */
tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
assert(tb_fw_config_info != NULL);
fconf_populate("TB_FW", tb_fw_config_info->config_addr);
fw_config_base = fw_config;
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
@ -135,6 +130,7 @@ void arm_bl2_plat_arch_setup(void)
#if ARM_CRYPTOCELL_INTEG
ARM_MAP_BL_COHERENT_RAM,
#endif
ARM_MAP_BL_CONFIG_REGION,
{0}
};
@ -151,7 +147,18 @@ void arm_bl2_plat_arch_setup(void)
void bl2_plat_arch_setup(void)
{
const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
arm_bl2_plat_arch_setup();
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", fw_config_base);
/* TB_FW_CONFIG was also loaded by BL1 */
tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
assert(tb_fw_config_info != NULL);
fconf_populate("TB_FW", tb_fw_config_info->config_addr);
}
int arm_bl2_handle_post_image_load(unsigned int image_id)

2
plat/arm/common/arm_dyn_cfg.c
View File

@ -203,7 +203,7 @@ void arm_bl2_dyn_cfg_init(void)
unsigned int i;
bl_mem_params_node_t *cfg_mem_params = NULL;
uintptr_t image_base;
size_t image_size;
uint32_t image_size;
const unsigned int config_ids[] = {
HW_CONFIG_ID,
SOC_FW_CONFIG_ID,

2
plat/arm/css/sgm/fdts/sgm_tb_fw_config.dts
View File

@ -8,7 +8,7 @@
/ {
/* Platform Config */
plat_arm_bl2 {
tb_fw-config {
compatible = "arm,tb_fw";
hw_config_addr = <0x0 0x83000000>;
hw_config_max_size = <0x01000000>;