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plat/arm: Move fconf population after the enablement of MMU 

In BL2, fw_config's population happened before the cache gets
enabled.
Hence to boost the performance, moved fw_config's population
after cache gets enabled (i.e. after MMU gets enabled).

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2e75cabd76b1cb7a660f6b72f409ab40d2877284
This commit is contained in:
Manish V Badarkhe 2020-07-16 05:45:25 +01:00 committed by Manish V Badarkhe
parent f441718936
commit a07c101a4d
5 changed files with 83 additions and 14 deletions
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9
include/plat/arm/common/arm_def.h
View File

@ -294,12 +294,19 @@
#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
V2M_FLASH_BLOCK_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define ARM_BL_REGIONS 6
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)

18
plat/arm/board/a5ds/include/platform_def.h
View File

@ -151,11 +151,19 @@
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define ARM_BL_REGIONS 6
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
@ -194,6 +202,12 @@
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*
* Define limit of firmware configuration memory:
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
@ -221,6 +235,8 @@
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ (PAGE_SIZE / 2U))
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)

23
plat/arm/board/corstone700/common/include/platform_def.h
View File

@ -92,11 +92,24 @@
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
/*
* Boot parameters passed from BL2 to BL31/BL32 are stored here
*/
#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ (PAGE_SIZE / 2U))
/*
* Define limit of firmware configuration memory:
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 2
#define ARM_BL_REGIONS 3
#define PLAT_ARM_MMAP_ENTRIES 8
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
@ -201,6 +214,14 @@
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
#define CORSTONE700_DEVICE_BASE (0x1A000000)
#define CORSTONE700_DEVICE_SIZE (0x26000000)
#define CORSTONE700_MAP_DEVICE MAP_REGION_FLAT( \

22
plat/arm/board/fvp_ve/include/platform_def.h
View File

@ -120,11 +120,20 @@
MT_DEVICE | MT_RW | MT_SECURE)
#endif
/*
* Map the region for device tree configuration with read and write permissions
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The max number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU.
*/
#define ARM_BL_REGIONS 5
#define ARM_BL_REGIONS 6
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
@ -173,7 +182,14 @@
* and limit. Leave enough space of BL2 meminfo.
*/
#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
+ (PAGE_SIZE / 2U))
/*
* Define limit of firmware configuration memory:
* ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
*/
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
/*******************************************************************************
* BL1 specific defines.
@ -205,6 +221,8 @@
/* Put BL32 below BL2 in NS DRAM.*/
#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ (PAGE_SIZE / 2U))
#define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
- PLAT_ARM_MAX_BL32_SIZE)

25
plat/arm/common/arm_bl2_setup.c
View File

@ -26,6 +26,9 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
/* Base address of fw_config received from BL1 */
static uintptr_t fw_config_base;
/*
* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
* for `meminfo_t` data structure and fw_configs passed from BL1.
@ -57,21 +60,13 @@ CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
void arm_bl2_early_platform_setup(uintptr_t fw_config,
struct meminfo *mem_layout)
{
const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
/* Initialize the console to provide early debug support */
arm_console_boot_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", fw_config);
/* TB_FW_CONFIG was also loaded by BL1 */
tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
assert(tb_fw_config_info != NULL);
fconf_populate("TB_FW", tb_fw_config_info->config_addr);
fw_config_base = fw_config;
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
@ -135,6 +130,7 @@ void arm_bl2_plat_arch_setup(void)
#if ARM_CRYPTOCELL_INTEG
ARM_MAP_BL_COHERENT_RAM,
#endif
ARM_MAP_BL_CONFIG_REGION,
{0}
};
@ -151,7 +147,18 @@ void arm_bl2_plat_arch_setup(void)
void bl2_plat_arch_setup(void)
{
const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
arm_bl2_plat_arch_setup();
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", fw_config_base);
/* TB_FW_CONFIG was also loaded by BL1 */
tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
assert(tb_fw_config_info != NULL);
fconf_populate("TB_FW", tb_fw_config_info->config_addr);
}
int arm_bl2_handle_post_image_load(unsigned int image_id)