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fix(drivers/marvell/comphy-3700): fix comments about selector register values 

The comments about selector register values are wrong.

Bit 0 configures only lane 1, bit 4 only lane 0, and bit 8 lanes 0 and
2.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Iffe42374f92654ebe570557e0d462204439cfa31
This commit is contained in:
Marek Behún 2021-12-02 19:23:09 +01:00
parent 4bcfd8c02e
commit 71183ef665
1 changed files with 3 additions and 3 deletions
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6
drivers/marvell/comphy/phy-comphy-3700.h
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@ -13,11 +13,11 @@
#define REG_16_BIT_MASK 0xFFFF
#define COMPHY_SELECTOR_PHY_REG 0xFC
/* bit0: 0: Lane0 is GBE0; 1: Lane1 is PCIE */
/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIE */
#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
/* bit4: 0: Lane1 is GBE1; 1: Lane1 is USB3 */
/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
/* bit8: 0: Lane1 is USB, Lane2 is SATA; 1: Lane2 is USB3 */
/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
/* SATA PHY register offset */