MISRA fixes for Cortex A75 AMU implementation
Change-Id: I61c9fdfda0c0b3c3ec6249519db23602cf4c2100 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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@ -28,9 +28,9 @@
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* enable this with suitable programming.
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* enable this with suitable programming.
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*/
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*/
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#define CORTEX_A75_AMU_NR_COUNTERS 5
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#define CORTEX_A75_AMU_NR_COUNTERS U(5)
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#define CORTEX_A75_AMU_GROUP0_MASK 0x7
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#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
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#define CORTEX_A75_AMU_GROUP1_MASK (0 << 3)
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#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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#include <stdint.h>
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@ -10,14 +10,14 @@
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static void *cortex_a75_context_save(const void *arg)
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static void *cortex_a75_context_save(const void *arg)
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{
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{
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if (midr_match(CORTEX_A75_MIDR))
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if (midr_match(CORTEX_A75_MIDR) != 0)
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cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
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cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
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return 0;
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return 0;
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}
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}
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static void *cortex_a75_context_restore(const void *arg)
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static void *cortex_a75_context_restore(const void *arg)
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{
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{
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if (midr_match(CORTEX_A75_MIDR))
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if (midr_match(CORTEX_A75_MIDR) != 0)
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cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
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cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
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return 0;
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return 0;
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}
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}
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@ -8,11 +8,11 @@
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#include <platform.h>
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#include <platform.h>
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#include <pubsub_events.h>
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#include <pubsub_events.h>
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#define CPUAMU_NR_COUNTERS 5
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#define CPUAMU_NR_COUNTERS 5U
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struct amu_ctx {
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struct amu_ctx {
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uint64_t cnts[CPUAMU_NR_COUNTERS];
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uint64_t cnts[CPUAMU_NR_COUNTERS];
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uint16_t mask;
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unsigned int mask;
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};
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};
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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@ -21,7 +21,7 @@ int midr_match(unsigned int cpu_midr)
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{
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{
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unsigned int midr, midr_mask;
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unsigned int midr, midr_mask;
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midr = read_midr();
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midr = (unsigned int)read_midr();
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
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return ((midr & midr_mask) == (cpu_midr & midr_mask));
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return ((midr & midr_mask) == (cpu_midr & midr_mask));
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@ -30,7 +30,7 @@ int midr_match(unsigned int cpu_midr)
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void cpuamu_context_save(unsigned int nr_counters)
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void cpuamu_context_save(unsigned int nr_counters)
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{
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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int i;
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unsigned int i;
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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@ -49,7 +49,7 @@ void cpuamu_context_save(unsigned int nr_counters)
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void cpuamu_context_restore(unsigned int nr_counters)
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void cpuamu_context_restore(unsigned int nr_counters)
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{
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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int i;
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unsigned int i;
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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