Tegra194: update cache operations supported by the ROC
This patch updates the cache ops to use system registers in order to trigger cache flush/clean operations. Change-Id: I888abad22f22b8a33c7193b991fad8c4a78030d0 Signed-off-by: Steven Kao <skao@nvidia.com>
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@ -75,5 +75,8 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
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void nvg_set_request_data(uint64_t req, uint64_t data);
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void nvg_set_request(uint64_t req);
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uint64_t nvg_get_result(void);
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uint64_t nvg_cache_clean(void);
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uint64_t nvg_cache_clean_inval(void);
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uint64_t nvg_cache_inval_all(void);
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#endif /* __MCE_PRIVATE_H__ */
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@ -10,6 +10,9 @@
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.globl nvg_set_request_data
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.globl nvg_set_request
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.globl nvg_get_result
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.globl nvg_cache_clean
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.globl nvg_cache_clean_inval
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.globl nvg_cache_inval_all
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/* void nvg_set_request_data(uint64_t req, uint64_t data) */
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func nvg_set_request_data
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@ -29,3 +32,21 @@ func nvg_get_result
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mrs x0, s3_0_c15_c1_3
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ret
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endfunc nvg_get_result
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/* uint64_t nvg_cache_clean(void) */
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func nvg_cache_clean
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mrs x0, s3_0_c15_c3_5
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ret
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endfunc nvg_cache_clean
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/* uint64_t nvg_cache_clean_inval(void) */
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func nvg_cache_clean_inval
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mrs x0, s3_0_c15_c3_6
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ret
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endfunc nvg_cache_clean_inval
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/* uint64_t nvg_cache_inval_all(void) */
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func nvg_cache_inval_all
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mrs x0, s3_0_c15_c3_7
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ret
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endfunc nvg_cache_inval_all
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@ -15,10 +15,8 @@
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#include <t194_nvg.h>
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#include <tegra_private.h>
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extern void nvg_set_request_data(uint64_t req, uint64_t data);
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extern void nvg_set_request(uint64_t req);
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extern uint64_t nvg_get_result(void);
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#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12
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#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU
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/*
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* Reports the major and minor version of this interface.
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*
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@ -306,41 +304,62 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
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/*
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* Cache clean operation for all CCPLEX caches.
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*
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* NVGDATA[0] cache_clean
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*/
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int32_t nvg_roc_clean_cache(void)
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{
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
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(uint64_t)CACHE_CLEAN_SET);
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int32_t ret = 0;
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return 0;
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/* check if cache flush through mts is supported */
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if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
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ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
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if (nvg_cache_clean() == 0U) {
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ERROR("%s: failed\n", __func__);
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ret = EINVAL;
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}
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} else {
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ret = EINVAL;
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}
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return ret;
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}
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/*
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* Cache clean and invalidate operation for all CCPLEX caches.
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*
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* NVGDATA[1] cache_clean_inval
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*/
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int32_t nvg_roc_flush_cache(void)
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{
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
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(uint64_t)CACHE_CLEAN_INVAL_SET);
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int32_t ret = 0;
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return 0;
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/* check if cache flush through mts is supported */
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if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
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ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
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if (nvg_cache_clean_inval() == 0U) {
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ERROR("%s: failed\n", __func__);
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ret = EINVAL;
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}
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} else {
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ret = EINVAL;
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}
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return ret;
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}
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/*
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* Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
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*
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* NVGDATA[2] cache_clean_inval_tr
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*/
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int32_t nvg_roc_clean_cache_trbits(void)
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{
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nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
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(uint64_t)CACHE_CLEAN_INVAL_TR_SET);
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int32_t ret = 0;
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return 0;
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/* check if cache flush through mts is supported */
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if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
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ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
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if (nvg_cache_inval_all() == 0U) {
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ERROR("%s: failed\n", __func__);
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ret = EINVAL;
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}
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} else {
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ret = EINVAL;
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}
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return ret;
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}
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/*
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