Merge changes from topic "jb/8.6-features" into integration
* changes: Enable ARMv8.6-ECV Self-Synch when booting to EL2 Enable ARMv8.6-FGT when booting to EL2
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737e7e74af
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@ -211,6 +211,17 @@
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#define PARANGE_0101 U(48)
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#define PARANGE_0110 U(52)
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#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
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#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
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#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
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#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
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#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
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#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
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#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
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#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
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#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
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#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
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#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
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#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
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@ -324,6 +335,8 @@
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#define SCR_TWEDEL_SHIFT U(30)
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#define SCR_TWEDEL_MASK ULL(0xf)
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#define SCR_TWEDEn_BIT (UL(1) << 29)
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#define SCR_ECVEN_BIT (U(1) << 28)
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#define SCR_FGTEN_BIT (U(1) << 27)
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#define SCR_ATA_BIT (U(1) << 26)
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#define SCR_FIEN_BIT (U(1) << 21)
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#define SCR_EEL2_BIT (U(1) << 18)
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@ -64,6 +64,18 @@ static inline bool is_armv8_6_twed_present(void)
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ID_AA64MMFR1_EL1_TWED_MASK) == ID_AA64MMFR1_EL1_TWED_SUPPORTED);
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}
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static inline bool is_armv8_6_fgt_present(void)
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{
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return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
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ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED;
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}
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static inline unsigned long int get_armv8_6_ecv_support(void)
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{
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return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_ECV_SHIFT) &
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ID_AA64MMFR0_EL1_ECV_MASK);
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}
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/*
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* Return MPAM version:
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*
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@ -173,11 +173,26 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
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* SCR_EL3.HCE: Enable HVC instructions if next execution state is
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* AArch64 and next EL is EL2, or if next execution state is AArch32 and
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* next mode is Hyp.
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* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
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* same conditions as HVC instructions and when the processor supports
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* ARMv8.6-FGT.
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* SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
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* CNTPOFF_EL2 register under the same conditions as HVC instructions
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* and when the processor supports ECV.
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*/
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if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
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|| ((GET_RW(ep->spsr) != MODE_RW_64)
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&& (GET_M32(ep->spsr) == MODE32_hyp))) {
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scr_el3 |= SCR_HCE_BIT;
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if (is_armv8_6_fgt_present()) {
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scr_el3 |= SCR_FGTEN_BIT;
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}
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if (get_armv8_6_ecv_support()
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== ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
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scr_el3 |= SCR_ECVEN_BIT;
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}
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}
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/* Enable S-EL2 if the next EL is EL2 and security state is secure */
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