rockchip/rk3399: remove unneeded DDR restore function
This removes the phy_dll_bypass_set function as it is unneeded. The values that function sets are saved during suspend, so the proper values will be restored on resume. Change-Id: I17542206c56e639ce8cb6375233145167441d4e2 Signed-off-by: Derek Basehore <dbasehore@chromium.org>
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@ -119,31 +119,6 @@ static __sramfunc void phy_pctrl_reset(uint32_t ch)
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sram_udelay(10);
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}
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static __sramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t hz)
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{
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if (hz <= 125 * MHz) {
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/* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
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mmio_setbits_32(PHY_REG(ch, 86), (0x3 << 2) << 8);
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mmio_setbits_32(PHY_REG(ch, 214), (0x3 << 2) << 8);
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mmio_setbits_32(PHY_REG(ch, 342), (0x3 << 2) << 8);
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mmio_setbits_32(PHY_REG(ch, 470), (0x3 << 2) << 8);
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/* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
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mmio_setbits_32(PHY_REG(ch, 547), (0x3 << 2) << 16);
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mmio_setbits_32(PHY_REG(ch, 675), (0x3 << 2) << 16);
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mmio_setbits_32(PHY_REG(ch, 803), (0x3 << 2) << 16);
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} else {
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/* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
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mmio_clrbits_32(PHY_REG(ch, 86), (0x3 << 2) << 8);
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mmio_clrbits_32(PHY_REG(ch, 214), (0x3 << 2) << 8);
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mmio_clrbits_32(PHY_REG(ch, 342), (0x3 << 2) << 8);
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mmio_clrbits_32(PHY_REG(ch, 470), (0x3 << 2) << 8);
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/* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
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mmio_clrbits_32(PHY_REG(ch, 547), (0x3 << 2) << 16);
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mmio_clrbits_32(PHY_REG(ch, 675), (0x3 << 2) << 16);
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mmio_clrbits_32(PHY_REG(ch, 803), (0x3 << 2) << 16);
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}
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}
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static __sramfunc void set_cs_training_index(uint32_t ch, uint32_t rank)
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{
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/* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */
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@ -721,7 +696,6 @@ __sramfunc void dmc_restore(void)
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retry:
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for (channel = 0; channel < sdram_params->num_channels; channel++) {
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phy_pctrl_reset(channel);
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phy_dll_bypass_set(channel, sdram_params->ddr_freq);
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if (channel >= sdram_params->num_channels)
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continue;
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