Merge changes from topic "allwinner_mmap" into integration
* changes: refactor(plat/allwinner): clean up platform definitions refactor(plat/allwinner): do not map BL32 DRAM at EL3 refactor(plat/allwinner): map SRAM as device memory by default refactor(plat/allwinner): rename static mmap region constant feat(bl_common): import BL_NOBITS_{BASE,END} when defined
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81e63f25ff
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@ -106,6 +106,10 @@ IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END);
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IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
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IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END);
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#endif
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#if SEPARATE_NOBITS_REGION
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IMPORT_SYM(uintptr_t, __NOBITS_START__, BL_NOBITS_BASE);
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IMPORT_SYM(uintptr_t, __NOBITS_END__, BL_NOBITS_END);
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#endif
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IMPORT_SYM(uintptr_t, __RW_END__, BL_END);
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#if defined(IMAGE_BL1)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -13,9 +13,6 @@
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#include <sunxi_mmap.h>
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/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
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#define SUNXI_SCP_SIZE 0x4000
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#ifdef SUNXI_BL31_IN_DRAM
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#define BL31_BASE SUNXI_DRAM_BASE
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@ -31,7 +28,6 @@
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#define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000)
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#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \
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SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
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#define SUNXI_SCP_BASE BL31_LIMIT
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/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
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#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
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@ -39,20 +35,23 @@
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#define MAX_XLAT_TABLES 1
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
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#define SUNXI_BL33_VIRT_BASE (SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE)
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#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE
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/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
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#define SUNXI_SCP_BASE BL31_LIMIT
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#define SUNXI_SCP_SIZE 0x4000
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#endif /* SUNXI_BL31_IN_DRAM */
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/* How much memory to reserve as secure for BL32, if configured */
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#define SUNXI_DRAM_SEC_SIZE (32U << 20)
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/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
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#define SUNXI_DRAM_MAP_SIZE (64U << 20)
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS)
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#define MAX_STATIC_MMAP_REGIONS 3
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#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
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#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
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(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
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@ -72,7 +71,6 @@
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_MMAP_REGIONS 5
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#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
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#ifndef SPD_none
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -14,17 +14,11 @@
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
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static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
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MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
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MT_RW_DATA | MT_SECURE),
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#ifdef SUNXI_SCP_BASE
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MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
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#endif
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MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
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MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
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MT_RW_DATA | MT_SECURE),
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MAP_REGION(PRELOADED_BL33_BASE, SUNXI_BL33_VIRT_BASE,
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SUNXI_DRAM_MAP_SIZE, MT_RW_DATA | MT_NS),
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{},
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@ -40,12 +34,24 @@ void sunxi_configure_mmu_el3(int flags)
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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mmap_add_region(BL_CODE_END, BL_CODE_END,
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BL_END - BL_CODE_END,
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MT_RW_DATA | MT_SECURE);
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#if SEPARATE_CODE_AND_RODATA
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mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
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BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE);
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#endif
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#if SEPARATE_NOBITS_REGION
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mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
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BL_NOBITS_END - BL_NOBITS_BASE,
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MT_RW_DATA | MT_SECURE);
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#endif
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#if USE_COHERENT_MEM
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
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#endif
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mmap_add(sunxi_mmap);
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init_xlat_tables();
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@ -212,7 +212,6 @@ int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
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uint32_t offset = SUNXI_SCP_BASE - vector;
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mmio_write_32(vector, offset >> 2);
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clean_dcache_range(vector, sizeof(uint32_t));
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}
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/* Take the SCP out of reset. */
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@ -244,7 +244,6 @@ void sunxi_cpu_power_off_self(void)
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* in instruction granularity (32 bits).
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*/
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mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
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clean_dcache_range(arisc_reset_vec, 4);
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/* De-assert the arisc reset line to let it run. */
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mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
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