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refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants 

According to the functional specification, the register at offset 0x48
is called Idle Sync Enable, not Unit Control or some such.

Rename the constants.

Only bit 12 of this register is defined, all other bits are reserved.
But for some reason the code needs the default value of the other bits,
so we also rename constant UNIT_CTRL_DEFAULT_VALUE to
IDLE_SYNC_EN_DEFAULT_VALUE.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Ia4f80f945a8f31c190cd9a1875d50d892e72825f
This commit is contained in:
Marek Behún 2021-12-08 00:15:29 +01:00
parent 3f9a089297
commit 86f6b55d47
2 changed files with 7 additions and 7 deletions
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8
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -725,8 +725,8 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
/*
* 9. Enable idle sync
*/
data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
usb3_reg_set(reg_base, COMPHY_UNIT_CTRL, data, REG_16_BIT_MASK);
data = IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN;
usb3_reg_set(reg_base, COMPHY_IDLE_SYNC_EN, data, REG_16_BIT_MASK);
/*
* 10. Enable the output of 500M clock
@ -839,8 +839,8 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
CFG_PM_RXDLOZ_WAIT_MASK));
/* 5. Enable idle sync */
reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
reg_set16(IDLE_SYNC_EN_ADDR(PCIE) + COMPHY_SD_ADDR,
IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
/* 6. Enable the output of 100M/125M/500M clock */
reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,

6
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -117,10 +117,10 @@ enum {
#define COMPHY_GEN3_SET2 0x3f
#define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit))
#define COMPHY_UNIT_CTRL 0x48
#define UNIT_CTRL_ADDR(unit) (COMPHY_UNIT_CTRL * PHY_SHFT(unit))
#define COMPHY_IDLE_SYNC_EN 0x48
#define IDLE_SYNC_EN_ADDR(unit) (COMPHY_IDLE_SYNC_EN * PHY_SHFT(unit))
#define IDLE_SYNC_EN BIT(12)
#define UNIT_CTRL_DEFAULT_VALUE 0x60
#define IDLE_SYNC_EN_DEFAULT_VALUE 0x60
#define COMPHY_MISC_REG0 0x4F
#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0 * PHY_SHFT(unit))