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rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error 

As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1
register, it need set the write_mask bit (bit16 ~ bit31), but as
we test, it not need it. So need to correct the setting way, otherwise
it will set wrong value to this register.

Signed-off-by: Lin Huang <hl@rock-chips.com>
This commit is contained in:
Lin Huang 2016-12-30 13:53:25 +08:00 committed by Xing Zheng
parent 175476f9e5
commit 87b5c17f91
1 changed files with 2 additions and 3 deletions
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5
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
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@ -52,9 +52,8 @@ void m0_init(void)
BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
0xf, 0));
/* gating disable for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0,
BITS_WITH_WMASK(0x3, 0x3, 0));
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
/*
* To switch the parent to xin24M and div == 1,