Merge pull request #845 from vwadekar/tegra-changes-from-downstream-v1
Tegra changes from downstream v1
This commit is contained in:
commit
87bf3c6249
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@ -62,6 +62,22 @@ TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31'
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Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>'
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to the build command line.
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The Tegra platform code expects a pointer to the following platform specific
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structure via 'x1' register from the BL2 layer which is used by the
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bl31_early_platform_setup() handler to extract the TZDRAM carveout base and
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size for loading the Trusted OS and the UART port ID to be used. The Tegra
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memory controller driver programs this base/size in order to restrict NS
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accesses.
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typedef struct plat_params_from_bl2 {
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/* TZ memory size */
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uint64_t tzdram_size;
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/* TZ memory base */
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uint64_t tzdram_base;
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/* UART port ID */
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int uart_id;
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} plat_params_from_bl2_t;
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Power Management
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================
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The PSCI implementation expects each platform to expose the 'power state'
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@ -31,8 +31,15 @@
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#ifndef __DENVER_H__
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#define __DENVER_H__
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/* MIDR for Denver v1.0 */
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#define DENVER_1_0_MIDR 0x4E0F0000
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/* MIDR values for Denver */
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#define DENVER_MIDR_PN0 0x4E0F0000
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#define DENVER_MIDR_PN1 0x4E0F0010
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#define DENVER_MIDR_PN2 0x4E0F0020
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#define DENVER_MIDR_PN3 0x4E0F0030
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#define DENVER_MIDR_PN4 0x4E0F0040
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/* Implementer code in the MIDR register */
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#define DENVER_IMPL 0x4E
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/* CPU state ids - implementation defined */
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#define DENVER_CPU_STATE_POWER_DOWN 0x3
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@ -163,7 +163,27 @@ func denver_cpu_reg_dump
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ret
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endfunc denver_cpu_reg_dump
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declare_cpu_ops denver, DENVER_1_0_MIDR, \
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declare_cpu_ops denver, DENVER_MIDR_PN0, \
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denver_reset_func, \
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denver_core_pwr_dwn, \
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denver_cluster_pwr_dwn
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declare_cpu_ops denver, DENVER_MIDR_PN1, \
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denver_reset_func, \
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denver_core_pwr_dwn, \
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denver_cluster_pwr_dwn
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declare_cpu_ops denver, DENVER_MIDR_PN2, \
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denver_reset_func, \
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denver_core_pwr_dwn, \
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denver_cluster_pwr_dwn
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declare_cpu_ops denver, DENVER_MIDR_PN3, \
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denver_reset_func, \
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denver_core_pwr_dwn, \
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denver_cluster_pwr_dwn
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declare_cpu_ops denver, DENVER_MIDR_PN4, \
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denver_reset_func, \
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denver_core_pwr_dwn, \
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denver_cluster_pwr_dwn
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@ -35,6 +35,22 @@
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#include <cortex_a53.h>
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#include <tegra_def.h>
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#define MIDR_PN_CORTEX_A57 0xD07
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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/* Global functions */
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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@ -50,6 +66,7 @@
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.globl tegra_sec_entry_point
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.globl ns_image_entrypoint
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.globl tegra_bl31_phys_base
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.globl tegra_console_base
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/* ---------------------
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* Common CPU init code
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@ -57,7 +74,18 @@
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*/
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.macro cpu_init_common
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#if ENABLE_L2_DYNAMIC_RETENTION
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/* ------------------------------------------------
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* We enable procesor retention and L2/CPUECTLR NS
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* access for A57 CPUs only.
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* ------------------------------------------------
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*/
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mrs x0, midr_el1
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mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
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and x0, x0, x1
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lsr x0, x0, #MIDR_PN_SHIFT
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cmp x0, #MIDR_PN_CORTEX_A57
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b.ne 1f
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/* ---------------------------
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* Enable processor retention
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* ---------------------------
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@ -68,18 +96,14 @@
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orr x0, x0, x1
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msr L2ECTLR_EL1, x0
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isb
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#endif
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#if ENABLE_CPU_DYNAMIC_RETENTION
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mrs x0, CPUECTLR_EL1
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mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
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bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
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orr x0, x0, x1
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msr CPUECTLR_EL1, x0
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isb
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#endif
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#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
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/* -------------------------------------------------------
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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@ -88,13 +112,12 @@
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msr actlr_el3, x0
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msr actlr_el2, x0
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isb
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#endif
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/* --------------------------------
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* Enable the cycle count register
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* --------------------------------
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*/
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mrs x0, pmcr_el0
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1: mrs x0, pmcr_el0
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ubfx x0, x0, #11, #5 // read PMCR.N field
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mov x1, #1
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lsl x0, x1, x0
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@ -157,6 +180,20 @@ func plat_get_my_entrypoint
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* int platform_get_core_pos(int mpidr);
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*
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* With this function: CorePos = (ClusterId * 4) +
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* CoreId
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* -----------------------------------------------------
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*/
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func platform_get_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc platform_get_core_pos
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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@ -190,7 +227,8 @@ endfunc platform_mem_init
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, TEGRA_BOOT_UART_BASE
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adr x0, tegra_console_base
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ldr x0, [x0]
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mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ
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mov_imm x2, TEGRA_CONSOLE_BAUDRATE
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b console_core_init
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@ -204,7 +242,8 @@ endfunc plat_crash_console_init
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, TEGRA_BOOT_UART_BASE
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adr x1, tegra_console_base
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ldr x1, [x1]
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b console_core_putc
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endfunc plat_crash_console_putc
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@ -366,3 +405,10 @@ ns_image_entrypoint:
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*/
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tegra_bl31_phys_base:
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.quad 0
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/* --------------------------------------------------
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* UART controller base for console init
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* --------------------------------------------------
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*/
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tegra_console_base:
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.quad 0
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@ -31,8 +31,9 @@
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#include <arch_helpers.h>
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#include <assert.h>
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#include <debug.h>
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#include <mmio.h>
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#include <memctrl.h>
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#include <memctrl_v1.h>
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#include <mmio.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <utils.h>
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@ -54,7 +55,7 @@ void tegra_memctrl_setup(void)
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* Setup the Memory controller to allow only secure accesses to
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* the TZDRAM carveout
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*/
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INFO("Configuring SMMU\n");
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INFO("Tegra Memory Controller (v1)\n");
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/* allow translations for all MC engines */
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tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0,
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@ -37,6 +37,7 @@
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#include <cortex_a57.h>
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#include <cortex_a53.h>
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#include <debug.h>
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#include <denver.h>
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#include <errno.h>
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#include <memctrl.h>
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#include <mmio.h>
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@ -54,6 +55,7 @@ extern unsigned long __RO_END__;
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extern unsigned long __BL31_END__;
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t tegra_console_base;
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/*
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* The next 3 constants identify the extents of the code, RO data region and the
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@ -110,28 +112,47 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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{
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plat_params_from_bl2_t *plat_params =
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(plat_params_from_bl2_t *)plat_params_from_bl2;
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/*
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* Configure the UART port to be used as the console
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*/
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console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ,
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TEGRA_CONSOLE_BAUDRATE);
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/* Initialise crash console */
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plat_crash_console_init();
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#if DEBUG
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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#endif
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/*
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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assert(from_bl2->bl33_ep_info);
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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if (from_bl2->bl32_ep_info)
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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/*
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* Parse platform specific parameters - TZDRAM aperture size
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* Parse platform specific parameters - TZDRAM aperture base and size
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*/
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if (plat_params)
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assert(plat_params);
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plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
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plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
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plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
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/*
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* Get the base address of the UART controller to be used for the
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* console
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*/
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assert(plat_params->uart_id);
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tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
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/*
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* Configure the UART port to be used as the console
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*/
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assert(tegra_console_base);
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console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
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TEGRA_CONSOLE_BAUDRATE);
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/* Initialise crash console */
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plat_crash_console_init();
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INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
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"Denver" : "ARM", read_mpidr());
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}
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/*******************************************************************************
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@ -159,7 +180,7 @@ void bl31_platform_setup(void)
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
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tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
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plat_bl31_params_from_bl2.tzdram_size);
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/* Set the next EL to be AArch64 */
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@ -168,6 +189,8 @@ void bl31_platform_setup(void)
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/* Initialize the gic cpu and distributor interfaces */
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tegra_gic_setup();
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INFO("BL3-1: Tegra platform setup complete\n");
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}
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/*******************************************************************************
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@ -215,6 +238,8 @@ void bl31_plat_arch_setup(void)
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/* enable the MMU */
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enable_mmu_el3(0);
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INFO("BL3-1: Tegra: MMU enabled\n");
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}
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/*******************************************************************************
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@ -54,12 +54,9 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
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plat/common/aarch64/platform_mp_stack.S \
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plat/common/plat_psci_common.c \
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${COMMON_DIR}/aarch64/tegra_helpers.S \
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${COMMON_DIR}/drivers/memctrl/memctrl.c \
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${COMMON_DIR}/drivers/pmc/pmc.c \
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${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
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${COMMON_DIR}/tegra_bl31_setup.c \
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${COMMON_DIR}/tegra_delay_timer.c \
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${COMMON_DIR}/tegra_gic.c \
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${COMMON_DIR}/tegra_pm.c \
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${COMMON_DIR}/tegra_sip_calls.c \
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${COMMON_DIR}/tegra_topology.c
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@ -174,7 +174,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
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* Security configuration to allow DRAM/device access.
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*/
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plat_params = bl31_get_plat_params();
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tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
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tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
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plat_params->tzdram_size);
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}
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@ -31,53 +31,6 @@
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#ifndef __MEMCTRL_H__
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#define __MEMCTRL_H__
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#include <mmio.h>
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#include <tegra_def.h>
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/* SMMU registers */
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#define MC_SMMU_CONFIG_0 0x10
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#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0
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#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1
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#define MC_SMMU_TLB_CONFIG_0 0x14
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#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010
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#define MC_SMMU_PTC_CONFIG_0 0x18
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#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f
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#define MC_SMMU_TLB_FLUSH_0 0x30
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#define TLB_FLUSH_VA_MATCH_ALL 0
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#define TLB_FLUSH_ASID_MATCH_DISABLE 0
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#define TLB_FLUSH_ASID_MATCH_SHIFT 31
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#define MC_SMMU_TLB_FLUSH_ALL \
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(TLB_FLUSH_VA_MATCH_ALL | \
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(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
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#define MC_SMMU_PTC_FLUSH_0 0x34
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#define MC_SMMU_PTC_FLUSH_ALL 0
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#define MC_SMMU_ASID_SECURITY_0 0x38
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#define MC_SMMU_ASID_SECURITY 0
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#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228
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#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c
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#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230
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#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234
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#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
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#define MC_SMMU_TRANSLATION_ENABLE (~0)
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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static inline uint32_t tegra_mc_read_32(uint32_t off)
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{
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return mmio_read_32(TEGRA_MC_BASE + off);
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}
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static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
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{
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mmio_write_32(TEGRA_MC_BASE + off, val);
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}
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void tegra_memctrl_setup(void);
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void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
|
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void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
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@ -0,0 +1,81 @@
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/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __MEMCTRLV1_H__
|
||||
#define __MEMCTRLV1_H__
|
||||
|
||||
#include <mmio.h>
|
||||
#include <tegra_def.h>
|
||||
|
||||
/* SMMU registers */
|
||||
#define MC_SMMU_CONFIG_0 0x10
|
||||
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0
|
||||
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1
|
||||
#define MC_SMMU_TLB_CONFIG_0 0x14
|
||||
#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010
|
||||
#define MC_SMMU_PTC_CONFIG_0 0x18
|
||||
#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f
|
||||
#define MC_SMMU_TLB_FLUSH_0 0x30
|
||||
#define TLB_FLUSH_VA_MATCH_ALL 0
|
||||
#define TLB_FLUSH_ASID_MATCH_DISABLE 0
|
||||
#define TLB_FLUSH_ASID_MATCH_SHIFT 31
|
||||
#define MC_SMMU_TLB_FLUSH_ALL \
|
||||
(TLB_FLUSH_VA_MATCH_ALL | \
|
||||
(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
|
||||
#define MC_SMMU_PTC_FLUSH_0 0x34
|
||||
#define MC_SMMU_PTC_FLUSH_ALL 0
|
||||
#define MC_SMMU_ASID_SECURITY_0 0x38
|
||||
#define MC_SMMU_ASID_SECURITY 0
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
|
||||
#define MC_SMMU_TRANSLATION_ENABLE (~0)
|
||||
|
||||
/* TZDRAM carveout configuration registers */
|
||||
#define MC_SECURITY_CFG0_0 0x70
|
||||
#define MC_SECURITY_CFG1_0 0x74
|
||||
|
||||
/* Video Memory carveout configuration registers */
|
||||
#define MC_VIDEO_PROTECT_BASE 0x648
|
||||
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
|
||||
|
||||
static inline uint32_t tegra_mc_read_32(uint32_t off)
|
||||
{
|
||||
return mmio_read_32(TEGRA_MC_BASE + off);
|
||||
}
|
||||
|
||||
static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
|
||||
{
|
||||
mmio_write_32(TEGRA_MC_BASE + off, val);
|
||||
}
|
||||
|
||||
#endif /* __MEMCTRLV1_H__ */
|
|
@ -84,8 +84,6 @@
|
|||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define ADDR_SPACE_SIZE (1ull << 32)
|
||||
#define MAX_XLAT_TABLES 3
|
||||
#define MAX_MMAP_REGIONS 8
|
||||
|
||||
/*******************************************************************************
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
|
|
|
@ -70,6 +70,15 @@
|
|||
******************************************************************************/
|
||||
#define TEGRA_EVP_BASE 0x6000F000
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra UART controller base addresses
|
||||
******************************************************************************/
|
||||
#define TEGRA_UARTA_BASE 0x70006000
|
||||
#define TEGRA_UARTB_BASE 0x70006040
|
||||
#define TEGRA_UARTC_BASE 0x70006200
|
||||
#define TEGRA_UARTD_BASE 0x70006300
|
||||
#define TEGRA_UARTE_BASE 0x70006400
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra Power Mgmt Controller constants
|
||||
******************************************************************************/
|
||||
|
|
|
@ -47,20 +47,6 @@
|
|||
******************************************************************************/
|
||||
#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
|
||||
|
||||
/*******************************************************************************
|
||||
* Implementation defined ACTLR_EL3 bit definitions
|
||||
******************************************************************************/
|
||||
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
|
||||
#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
|
||||
#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
|
||||
#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
|
||||
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
|
||||
#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
|
||||
ACTLR_EL3_L2ECTLR_BIT | \
|
||||
ACTLR_EL3_L2CTLR_BIT | \
|
||||
ACTLR_EL3_CPUECTLR_BIT | \
|
||||
ACTLR_EL3_CPUACTLR_BIT)
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC memory map
|
||||
******************************************************************************/
|
||||
|
@ -109,6 +95,15 @@
|
|||
******************************************************************************/
|
||||
#define TEGRA_EVP_BASE 0x6000F000
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra UART controller base addresses
|
||||
******************************************************************************/
|
||||
#define TEGRA_UARTA_BASE 0x70006000
|
||||
#define TEGRA_UARTB_BASE 0x70006040
|
||||
#define TEGRA_UARTC_BASE 0x70006200
|
||||
#define TEGRA_UARTD_BASE 0x70006300
|
||||
#define TEGRA_UARTE_BASE 0x70006400
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra Power Mgmt Controller constants
|
||||
******************************************************************************/
|
||||
|
|
|
@ -43,7 +43,12 @@
|
|||
#define TEGRA_DRAM_END 0x27FFFFFFF
|
||||
|
||||
typedef struct plat_params_from_bl2 {
|
||||
/* TZ memory size */
|
||||
uint64_t tzdram_size;
|
||||
/* TZ memory base */
|
||||
uint64_t tzdram_base;
|
||||
/* UART port ID */
|
||||
int uart_id;
|
||||
} plat_params_from_bl2_t;
|
||||
|
||||
/* Declarations for plat_psci_handlers.c */
|
||||
|
@ -52,6 +57,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
|
|||
|
||||
/* Declarations for plat_setup.c */
|
||||
const mmap_region_t *plat_get_mmio_map(void);
|
||||
uint32_t plat_get_console_from_id(int id);
|
||||
|
||||
/* Declarations for plat_secondary.c */
|
||||
void plat_secondary_setup(void);
|
||||
|
|
|
@ -78,3 +78,31 @@ unsigned int plat_get_syscnt_freq2(void)
|
|||
{
|
||||
return 12000000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Maximum supported UART controllers
|
||||
******************************************************************************/
|
||||
#define TEGRA132_MAX_UART_PORTS 5
|
||||
|
||||
/*******************************************************************************
|
||||
* This variable holds the UART port base addresses
|
||||
******************************************************************************/
|
||||
static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
|
||||
0, /* undefined - treated as an error case */
|
||||
TEGRA_UARTA_BASE,
|
||||
TEGRA_UARTB_BASE,
|
||||
TEGRA_UARTC_BASE,
|
||||
TEGRA_UARTD_BASE,
|
||||
TEGRA_UARTE_BASE,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Retrieve the UART controller base to be used as the console
|
||||
******************************************************************************/
|
||||
uint32_t plat_get_console_from_id(int id)
|
||||
{
|
||||
if (id > TEGRA132_MAX_UART_PORTS)
|
||||
return 0;
|
||||
|
||||
return tegra132_uart_addresses[id];
|
||||
}
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra SiP SMCs
|
||||
* Tegra132 SiP SMCs
|
||||
******************************************************************************/
|
||||
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
|
||||
#define TEGRA_SIP_AARCH_SWITCH 0x82000004
|
||||
|
@ -58,7 +58,7 @@
|
|||
/*******************************************************************************
|
||||
* This function is responsible for handling all SiP calls from the NS world
|
||||
******************************************************************************/
|
||||
uint64_t tegra_sip_handler(uint32_t smc_fid,
|
||||
uint64_t tegra132_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
|
@ -138,11 +138,11 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
|
|||
|
||||
/* Define a runtime service descriptor for fast SMC calls */
|
||||
DECLARE_RT_SVC(
|
||||
tegra_sip_fast,
|
||||
tegra132_sip_fast,
|
||||
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
NULL,
|
||||
tegra_sip_handler
|
||||
tegra132_sip_handler
|
||||
);
|
|
@ -28,9 +28,6 @@
|
|||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
TEGRA_BOOT_UART_BASE := 0x70006300
|
||||
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
|
||||
|
||||
TZDRAM_BASE := 0xF5C00000
|
||||
$(eval $(call add_define,TZDRAM_BASE))
|
||||
|
||||
|
@ -40,7 +37,16 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
|
|||
PLATFORM_MAX_CPUS_PER_CLUSTER := 2
|
||||
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
MAX_XLAT_TABLES := 3
|
||||
$(eval $(call add_define,MAX_XLAT_TABLES))
|
||||
|
||||
MAX_MMAP_REGIONS := 8
|
||||
$(eval $(call add_define,MAX_MMAP_REGIONS))
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/denver.S \
|
||||
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
|
||||
${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
|
||||
${SOC_DIR}/plat_psci_handlers.c \
|
||||
${SOC_DIR}/plat_sip_calls.c \
|
||||
${SOC_DIR}/plat_setup.c \
|
||||
${SOC_DIR}/plat_secondary.c
|
||||
|
|
|
@ -84,3 +84,31 @@ unsigned int plat_get_syscnt_freq2(void)
|
|||
{
|
||||
return 19200000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Maximum supported UART controllers
|
||||
******************************************************************************/
|
||||
#define TEGRA210_MAX_UART_PORTS 5
|
||||
|
||||
/*******************************************************************************
|
||||
* This variable holds the UART port base addresses
|
||||
******************************************************************************/
|
||||
static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = {
|
||||
0, /* undefined - treated as an error case */
|
||||
TEGRA_UARTA_BASE,
|
||||
TEGRA_UARTB_BASE,
|
||||
TEGRA_UARTC_BASE,
|
||||
TEGRA_UARTD_BASE,
|
||||
TEGRA_UARTE_BASE,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Retrieve the UART controller base to be used as the console
|
||||
******************************************************************************/
|
||||
uint32_t plat_get_console_from_id(int id)
|
||||
{
|
||||
if (id > TEGRA210_MAX_UART_PORTS)
|
||||
return 0;
|
||||
|
||||
return tegra210_uart_addresses[id];
|
||||
}
|
||||
|
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <bl_common.h>
|
||||
#include <context_mgmt.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <memctrl.h>
|
||||
#include <runtime_svc.h>
|
||||
#include <tegra_private.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra210 SiP SMCs
|
||||
******************************************************************************/
|
||||
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is responsible for handling all SiP calls from the NS world
|
||||
******************************************************************************/
|
||||
uint64_t tegra210_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
uint64_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
uint64_t flags)
|
||||
{
|
||||
uint32_t ns;
|
||||
int err;
|
||||
|
||||
/* Determine which security state this SMC originated from */
|
||||
ns = is_caller_non_secure(flags);
|
||||
if (!ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
switch (smc_fid) {
|
||||
|
||||
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
|
||||
|
||||
/* clean up the high bits */
|
||||
x1 = (uint32_t)x1;
|
||||
x2 = (uint32_t)x2;
|
||||
|
||||
/*
|
||||
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
|
||||
* or falls outside of the valid DRAM range
|
||||
*/
|
||||
err = bl31_check_ns_address(x1, x2);
|
||||
if (err)
|
||||
SMC_RET1(handle, err);
|
||||
|
||||
/*
|
||||
* Check if Video Memory is aligned to 1MB.
|
||||
*/
|
||||
if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
|
||||
ERROR("Unaligned Video Memory base address!\n");
|
||||
SMC_RET1(handle, -ENOTSUP);
|
||||
}
|
||||
|
||||
/* new video memory carveout settings */
|
||||
tegra_memctrl_videomem_setup(x1, x2);
|
||||
|
||||
SMC_RET1(handle, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
break;
|
||||
}
|
||||
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
}
|
||||
|
||||
/* Define a runtime service descriptor for fast SMC calls */
|
||||
DECLARE_RT_SVC(
|
||||
tegra210_sip_fast,
|
||||
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
NULL,
|
||||
tegra210_sip_handler
|
||||
);
|
|
@ -28,33 +28,30 @@
|
|||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
TEGRA_BOOT_UART_BASE := 0x70006000
|
||||
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
|
||||
|
||||
TZDRAM_BASE := 0xFDC00000
|
||||
$(eval $(call add_define,TZDRAM_BASE))
|
||||
|
||||
ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
|
||||
$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
|
||||
|
||||
ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
|
||||
$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
|
||||
|
||||
ENABLE_L2_DYNAMIC_RETENTION := 1
|
||||
$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION))
|
||||
|
||||
ENABLE_CPU_DYNAMIC_RETENTION := 1
|
||||
$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION))
|
||||
|
||||
PLATFORM_CLUSTER_COUNT := 2
|
||||
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
|
||||
|
||||
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
|
||||
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
MAX_XLAT_TABLES := 3
|
||||
$(eval $(call add_define,MAX_XLAT_TABLES))
|
||||
|
||||
MAX_MMAP_REGIONS := 8
|
||||
$(eval $(call add_define,MAX_MMAP_REGIONS))
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a57.S \
|
||||
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
|
||||
${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
|
||||
${SOC_DIR}/plat_psci_handlers.c \
|
||||
${SOC_DIR}/plat_sip_calls.c \
|
||||
${SOC_DIR}/plat_setup.c \
|
||||
${SOC_DIR}/plat_secondary.c
|
||||
|
||||
|
|
Loading…
Reference in New Issue