Merge "TF-A GICv2 driver: Introduce makefile" into integration
This commit is contained in:
joanna.farley
TrustedFirmware Code Review
commit
8828b1a9e0
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@ -1,9 +1,11 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#pragma message __FILE__ " is deprecated, use gicv2.mk instead"
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#include <assert.h>
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#include <drivers/arm/gic_common.h>
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@ -0,0 +1,340 @@
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/mmio.h>
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#include "../common/gic_common_private.h"
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/*******************************************************************************
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* GIC Distributor interface accessors for reading entire registers
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******************************************************************************/
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/*
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* Accessor to read the GIC Distributor IGROUPR corresponding to the interrupt
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* `id`, 32 interrupt ids at a time.
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*/
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unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> IGROUPR_SHIFT;
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return mmio_read_32(base + GICD_IGROUPR + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ISENABLER corresponding to the
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* interrupt `id`, 32 interrupt ids at a time.
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*/
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unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ISENABLER_SHIFT;
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return mmio_read_32(base + GICD_ISENABLER + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ICENABLER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ICENABLER_SHIFT;
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return mmio_read_32(base + GICD_ICENABLER + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ISPENDR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ISPENDR_SHIFT;
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return mmio_read_32(base + GICD_ISPENDR + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ICPENDR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ICPENDR_SHIFT;
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return mmio_read_32(base + GICD_ICPENDR + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ISACTIVER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ISACTIVER_SHIFT;
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return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ICACTIVER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ICACTIVER_SHIFT;
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return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor IPRIORITYR corresponding to the
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* interrupt `id`, 4 interrupt IDs at a time.
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*/
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unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> IPRIORITYR_SHIFT;
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return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor ICGFR corresponding to the
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* interrupt `id`, 16 interrupt IDs at a time.
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*/
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unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> ICFGR_SHIFT;
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return mmio_read_32(base + GICD_ICFGR + (n << 2));
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}
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/*
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* Accessor to read the GIC Distributor NSACR corresponding to the
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* interrupt `id`, 16 interrupt IDs at a time.
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*/
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unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id)
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{
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unsigned int n = id >> NSACR_SHIFT;
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return mmio_read_32(base + GICD_NSACR + (n << 2));
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}
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/*******************************************************************************
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* GIC Distributor interface accessors for writing entire registers
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******************************************************************************/
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/*
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* Accessor to write the GIC Distributor IGROUPR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> IGROUPR_SHIFT;
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mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ISENABLER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ISENABLER_SHIFT;
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mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ICENABLER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ICENABLER_SHIFT;
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mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ISPENDR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ISPENDR_SHIFT;
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mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ICPENDR corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ICPENDR_SHIFT;
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mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ISACTIVER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ISACTIVER_SHIFT;
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mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ICACTIVER corresponding to the
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* interrupt `id`, 32 interrupt IDs at a time.
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*/
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void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ICACTIVER_SHIFT;
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mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor IPRIORITYR corresponding to the
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* interrupt `id`, 4 interrupt IDs at a time.
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*/
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void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> IPRIORITYR_SHIFT;
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mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor ICFGR corresponding to the
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* interrupt `id`, 16 interrupt IDs at a time.
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*/
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void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> ICFGR_SHIFT;
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mmio_write_32(base + GICD_ICFGR + (n << 2), val);
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}
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/*
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* Accessor to write the GIC Distributor NSACR corresponding to the
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* interrupt `id`, 16 interrupt IDs at a time.
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*/
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void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned int n = id >> NSACR_SHIFT;
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mmio_write_32(base + GICD_NSACR + (n << 2), val);
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}
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/*******************************************************************************
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* GIC Distributor functions for accessing the GIC registers
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* corresponding to a single interrupt ID. These functions use bitwise
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* operations or appropriate register accesses to modify or return
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* the bit-field corresponding the single interrupt ID.
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******************************************************************************/
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unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_igroupr(base, id);
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return (reg_val >> bit_num) & 0x1U;
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}
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void gicd_set_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_igroupr(base, id);
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gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
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}
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void gicd_clr_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_igroupr(base, id);
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gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
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}
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void gicd_set_isenabler(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
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gicd_write_isenabler(base, id, (1U << bit_num));
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}
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void gicd_set_icenabler(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
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gicd_write_icenabler(base, id, (1U << bit_num));
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}
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void gicd_set_ispendr(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
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gicd_write_ispendr(base, id, (1U << bit_num));
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}
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void gicd_set_icpendr(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
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gicd_write_icpendr(base, id, (1U << bit_num));
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}
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unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_isactiver(base, id);
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return (reg_val >> bit_num) & 0x1U;
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}
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void gicd_set_isactiver(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
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gicd_write_isactiver(base, id, (1U << bit_num));
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}
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void gicd_set_icactiver(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
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gicd_write_icactiver(base, id, (1U << bit_num));
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}
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void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
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{
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uint8_t val = pri & GIC_PRI_MASK;
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mmio_write_8(base + GICD_IPRIORITYR + id, val);
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}
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void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg)
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{
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/* Interrupt configuration is a 2-bit field */
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unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
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unsigned int bit_shift = bit_num << 1;
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uint32_t reg_val = gicd_read_icfgr(base, id);
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/* Clear the field, and insert required configuration */
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reg_val &= ~(GIC_CFG_MASK << bit_shift);
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reg_val |= ((cfg & GIC_CFG_MASK) << bit_shift);
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gicd_write_icfgr(base, id, reg_val);
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}
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@ -0,0 +1,15 @@
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#
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# Copyright (c) 2020, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# No support for extended PPI and SPI range
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GIC_EXT_INTID := 0
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GICV2_SOURCES += drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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drivers/arm/gic/v2/gicdv2_helpers.c
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# Set GICv2 build option
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$(eval $(call add_define,GIC_EXT_INTID))
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@ -14,9 +14,10 @@ DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
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plat/arm/common/arm_dyn_cfg_helpers.c \
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common/fdt_wrappers.c
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A5DS_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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# Include GICv2 driver files
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include drivers/arm/gic/v2/gicv2.mk
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A5DS_GIC_SOURCES := ${GICV2_SOURCES} \
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plat/common/plat_gicv2.c \
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plat/arm/common/arm_gicv2.c
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|
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@ -25,9 +25,10 @@ PLAT_INCLUDES := -Iplat/arm/board/corstone700/common/include \
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NEED_BL32 := yes
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CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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# Include GICv2 driver files
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include drivers/arm/gic/v2/gicv2.mk
|
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CORSTONE700_GIC_SOURCES := ${GICV2_SOURCES} \
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plat/common/plat_gicv2.c \
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plat/arm/common/arm_gicv2.c
|
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|
||||
|
|
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@ -72,13 +72,10 @@ else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
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GIC_ENABLE_V4_EXTN := 0
|
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$(eval $(call add_define,GIC_ENABLE_V4_EXTN))
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# No support for extended PPI and SPI range
|
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GIC_EXT_INTID := 0
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$(eval $(call add_define,GIC_EXT_INTID))
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# Include GICv2 driver files
|
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include drivers/arm/gic/v2/gicv2.mk
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FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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FVP_GIC_SOURCES := ${GICV2_SOURCES} \
|
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plat/common/plat_gicv2.c \
|
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plat/arm/common/arm_gicv2.c
|
||||
|
||||
|
|
|
|||
|
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@ -11,10 +11,11 @@ $(eval $(call add_define,FVP_VE_USE_SP804_TIMER))
|
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BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
|
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endif
|
||||
|
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FVP_VE_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
plat/common/plat_gicv2.c \
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# Include GICv2 driver files
|
||||
include drivers/arm/gic/v2/gicv2.mk
|
||||
|
||||
FVP_VE_GIC_SOURCES := ${GICV2_SOURCES} \
|
||||
plat/common/plat_gicv2.c \
|
||||
plat/arm/common/arm_gicv2.c
|
||||
|
||||
FVP_VE_SECURITY_SOURCES := plat/arm/board/fvp_ve/fvp_ve_security.c
|
||||
|
|
|
|||
|
|
@ -4,9 +4,10 @@
|
|||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
# Include GICv2 driver files
|
||||
include drivers/arm/gic/v2/gicv2.mk
|
||||
|
||||
JUNO_GIC_SOURCES := ${GICV2_SOURCES} \
|
||||
plat/common/plat_gicv2.c \
|
||||
plat/arm/common/arm_gicv2.c
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
|
@ -20,9 +20,10 @@ TEGRA_GICv3_SOURCES := $(GICV3_SOURCES) \
|
|||
plat/common/plat_gicv3.c \
|
||||
${COMMON_DIR}/tegra_gicv3.c
|
||||
|
||||
TEGRA_GICv2_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
# Include GICv2 driver files
|
||||
include drivers/arm/gic/v2/gicv2.mk
|
||||
|
||||
TEGRA_GICv2_SOURCES := ${GICV2_SOURCES} \
|
||||
plat/common/plat_gicv2.c \
|
||||
${COMMON_DIR}/tegra_gicv2.c
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue