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Merge changes from topic "lm/improve_memory_layout" into integration 

* changes:
  DOC: Update ROMLIB page with memory impact info
  ROMLIB: Optimize memory layout when ROMLIB is used
This commit is contained in:
Sandrine Bailleux 2019-11-18 16:45:03 +00:00 committed by TrustedFirmware Code Review
parent 0d20514ec5 4685b64fc3
commit 896add4f1d
3 changed files with 25 additions and 6 deletions
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15
docs/components/romlib-design.rst
View File

@ -111,6 +111,21 @@ The calling sequence for a patched function is as follows:
BL image --> function
Memory impact
~~~~~~~~~~~~~
Using library at ROM will modify the memory layout of the BL images:
- The ROM library needs a page aligned RAM section to hold the RW data. This
section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros.
On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM.
This will have for effect to shift down all the BL images by 1 page.
- Depending on the functions moved to the ROM library, the size of the BL images
will be reduced.
For example: moving MbedTLS function into the ROM library reduces BL1 and
BL2, but not BL31.
- This change in BL images size can be taken into consideration to optimize the
memory layout when defining the BLx_BASE macros.
Build library at ROM
~~~~~~~~~~~~~~~~~~~~~

6
plat/arm/board/fvp/include/platform_def.h
View File

@ -94,9 +94,11 @@
#if USE_ROMLIB
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
#else
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
#endif
/*
@ -104,9 +106,9 @@
* little space for growth.
*/
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#else
# define PLAT_ARM_MAX_BL2_SIZE UL(0x11000)
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION)
#endif
/*

10
plat/arm/board/juno/include/platform_def.h
View File

@ -60,9 +60,11 @@
#if USE_ROMLIB
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
#define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000)
#else
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
#define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0)
#endif
/*
@ -127,14 +129,14 @@
*/
#if TRUSTED_BOARD_BOOT
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
# define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000)
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA
# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#else
# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000)
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#endif
#else
# define PLAT_ARM_MAX_BL2_SIZE UL(0xF000)
# define PLAT_ARM_MAX_BL2_SIZE (UL(0xF000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#endif
/*